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author | Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | 2023-05-30 10:11:35 -0400 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2023-08-23 17:52:21 +0200 |
commit | 96522cf9c71e461fd8df47ee746b2a28f785f085 (patch) | |
tree | c5d68e1f9128576c40f4b579aadcf19506ec3f48 /block | |
parent | 83c22663acb6f015aad8ad99f8734767699c5c69 (diff) | |
download | linux-96522cf9c71e461fd8df47ee746b2a28f785f085.tar.gz |
iommu/amd: Introduce Disable IRTE Caching Support
[ Upstream commit 66419036f68a838c00cbccacd6cb2e99da6e5710 ] An Interrupt Remapping Table (IRT) stores interrupt remapping configuration for each device. In a normal operation, the AMD IOMMU caches the table to optimize subsequent data accesses. This requires the IOMMU driver to invalidate IRT whenever it updates the table. The invalidation process includes issuing an INVALIDATE_INTERRUPT_TABLE command following by a COMPLETION_WAIT command. However, there are cases in which the IRT is updated at a high rate. For example, for IOMMU AVIC, the IRTE[IsRun] bit is updated on every vcpu scheduling (i.e. amd_iommu_update_ga()). On system with large amount of vcpus and VFIO PCI pass-through devices, the invalidation process could potentially become a performance bottleneck. Introducing a new kernel boot option: amd_iommu=irtcachedis which disables IRTE caching by setting the IRTCachedis bit in each IOMMU Control register, and bypass the IRT invalidation process. Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com> Co-developed-by: Alejandro Jimenez <alejandro.j.jimenez@oracle.com> Signed-off-by: Alejandro Jimenez <alejandro.j.jimenez@oracle.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Link: https://lore.kernel.org/r/20230530141137.14376-4-suravee.suthikulpanit@amd.com Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Sasha Levin <sashal@kernel.org>
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