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| author | Alexandre Torgue <alexandre.torgue@foss.st.com> | 2023-03-20 18:03:31 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2023-05-11 23:03:11 +0900 |
| commit | eb617ab023340c8874eeea5b57be9d39dcf5ae82 (patch) | |
| tree | b79d3839a3c59831fcc53ac111c5217f4e250ee6 /arch | |
| parent | 7ff92db0dd6f91e7c4dbbed21aae74bd5fc5123e (diff) | |
| download | linux-eb617ab023340c8874eeea5b57be9d39dcf5ae82.tar.gz | |
ARM: dts: stm32: fix spi1 pin assignment on stm32mp15
[ Upstream commit 1b9f0ec81af0012aae30aa3b4c711ad71d42e246 ]
Bank A and B IOs can't be handled by the pin controller 'Z'. This patch
assign spi1 pin definition to the correct controller.
Fixes: 9ad65d245b7b ("ARM: dts: stm32: stm32mp15-pinctrl: add spi1-1 pinmux group")
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index a9d2bec99014..e15a3b2a9b39 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1880,6 +1880,21 @@ }; }; + spi1_pins_b: spi1-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */ + <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */ + bias-disable; + }; + }; + spi2_pins_a: spi2-0 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */ @@ -2448,19 +2463,4 @@ bias-disable; }; }; - - spi1_pins_b: spi1-1 { - pins1 { - pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */ - <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */ - bias-disable; - }; - }; }; |