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| author | Robert Richter <robert.richter@amd.com> | 2010-02-23 18:14:58 +0100 |
|---|---|---|
| committer | Robert Richter <robert.richter@amd.com> | 2010-02-26 15:14:03 +0100 |
| commit | 98a2e73a0690b3610f049a64154d8145e5771713 (patch) | |
| tree | c58da8c5ffb458094af9681ec47f8b5e647f8d42 /arch/x86/oprofile/op_model_amd.c | |
| parent | ba52078e1917c5116c0802298d88ad0e54a6728b (diff) | |
| download | linux-98a2e73a0690b3610f049a64154d8145e5771713.tar.gz | |
oprofile/x86: warn user if a counter is already active
This patch generates a warning if a counter is already active. Implemented for AMD and P6 models. P4 is not supported. Cc: Naga Chumbalkar <nagananda.chumbalkar@hp.com> Cc: Shashi Belur <shashi-kiran.belur@hp.com> Cc: Tony Jones <tonyj@suse.de> Signed-off-by: Robert Richter <robert.richter@amd.com>
Diffstat (limited to 'arch/x86/oprofile/op_model_amd.c')
| -rw-r--r-- | arch/x86/oprofile/op_model_amd.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c index a9d194734a8e..ef9d735dea35 100644 --- a/arch/x86/oprofile/op_model_amd.c +++ b/arch/x86/oprofile/op_model_amd.c @@ -194,9 +194,18 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model, /* clear all counters */ for (i = 0; i < NUM_CONTROLS; ++i) { - if (unlikely(!msrs->controls[i].addr)) + if (unlikely(!msrs->controls[i].addr)) { + if (counter_config[i].enabled && !smp_processor_id()) + /* + * counter is reserved, this is on all + * cpus, so report only for cpu #0 + */ + op_x86_warn_reserved(i); continue; + } rdmsrl(msrs->controls[i].addr, val); + if (val & ARCH_PERFMON_EVENTSEL0_ENABLE) + op_x86_warn_in_use(i); val &= model->reserved; wrmsrl(msrs->controls[i].addr, val); } |