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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2022-03-21 11:11:48 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2022-03-21 11:11:48 -0700 |
| commit | d752e211146586dd654537a8b5282a6cf08a568f (patch) | |
| tree | c24ab95b06689374e951ba45028e8f6c04aef144 /arch/x86/include/asm/cpufeatures.h | |
| parent | 5e8919170ad683436a1a1305e1795dc1d56f8906 (diff) | |
| parent | 08f253ec3767bcfafc5d32617a92cee57c63968e (diff) | |
| download | linux-d752e211146586dd654537a8b5282a6cf08a568f.tar.gz | |
Merge tag 'x86_cpu_for_v5.18_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 cpu feature updates from Borislav Petkov: - Merge the AMD and Intel PPIN code into a shared one by both vendors. Add the PPIN number to sysfs so that sockets can be identified when replacement is needed - Minor fixes and cleanups * tag 'x86_cpu_for_v5.18_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/cpu: Clear SME feature flag when not in use x86/cpufeatures: Put the AMX macros in the word 18 block topology/sysfs: Add PPIN in sysfs under cpu topology topology/sysfs: Add format parameter to macro defining "show" functions for proc x86/cpu: Read/save PPIN MSR during initialization x86/cpu: X86_FEATURE_INTEL_PPIN finally has a CPUID bit x86/cpu: Merge Intel and AMD ppin_init() functions x86/CPU/AMD: Use default_groups in kobj_type
Diffstat (limited to 'arch/x86/include/asm/cpufeatures.h')
| -rw-r--r-- | arch/x86/include/asm/cpufeatures.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 65d147974f8d..f7436fccc076 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -299,9 +299,6 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ -#define X86_FEATURE_AMX_BF16 (18*32+22) /* AMX bf16 Support */ -#define X86_FEATURE_AMX_TILE (18*32+24) /* AMX tile Support */ -#define X86_FEATURE_AMX_INT8 (18*32+25) /* AMX int8 Support */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ @@ -390,7 +387,10 @@ #define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */ #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ #define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */ +#define X86_FEATURE_AMX_BF16 (18*32+22) /* AMX bf16 Support */ #define X86_FEATURE_AVX512_FP16 (18*32+23) /* AVX512 FP16 */ +#define X86_FEATURE_AMX_TILE (18*32+24) /* AMX tile Support */ +#define X86_FEATURE_AMX_INT8 (18*32+25) /* AMX int8 Support */ #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */ #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */ #define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */ |