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author | Sergey Shtylyov <s.shtylyov@omp.ru> | 2023-06-01 23:22:17 +0300 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2023-07-19 16:21:54 +0200 |
commit | f5d7f9e155175a099e47db40926cf82f46348bcc (patch) | |
tree | 3d9617a77581e0b8b74ce3e68e466d637d93cdd2 /arch/sh/include/mach-common/mach/highlander.h | |
parent | d199218881d7882442819e3c93c61e161ead6deb (diff) | |
download | linux-f5d7f9e155175a099e47db40926cf82f46348bcc.tar.gz |
sh: Avoid using IRQ0 on SH3 and SH4
[ Upstream commit a8ac2961148e8c720dc760f2e06627cd5c55a154 ] IRQ0 is no longer returned by platform_get_irq() and its ilk -- they now return -EINVAL instead. However, the kernel code supporting SH3/4-based SoCs still maps the IRQ #s starting at 0 -- modify that code to start the IRQ #s from 16 instead. The patch should mostly affect the AP-SH4A-3A/AP-SH4AD-0A boards as they indeed are using IRQ0 for the SMSC911x compatible Ethernet chip. Fixes: ce753ad1549c ("platform: finally disallow IRQ0 in platform_get_irq() and its ilk") Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Tested-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Link: https://lore.kernel.org/r/71105dbf-cdb0-72e1-f9eb-eeda8e321696@omp.ru Signed-off-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch/sh/include/mach-common/mach/highlander.h')
-rw-r--r-- | arch/sh/include/mach-common/mach/highlander.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/sh/include/mach-common/mach/highlander.h b/arch/sh/include/mach-common/mach/highlander.h index fb44c299d033..b12c79558422 100644 --- a/arch/sh/include/mach-common/mach/highlander.h +++ b/arch/sh/include/mach-common/mach/highlander.h @@ -176,7 +176,7 @@ #define IVDR_CK_ON 4 /* iVDR Clock ON */ #endif -#define HL_FPGA_IRQ_BASE 200 +#define HL_FPGA_IRQ_BASE (200 + 16) #define HL_NR_IRL 15 #define IRQ_AX88796 (HL_FPGA_IRQ_BASE + 0) |