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| author | Anup Patel <anup@brainfault.org> | 2018-12-04 19:25:06 +0530 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-12-17 10:23:46 -0800 |
| commit | 2b3f786408c5400705ed722ab2f3065e86272857 (patch) | |
| tree | 7759dcc86df915965c70b608b547a768b6a2257a /arch/riscv/configs | |
| parent | 7566ec393f4161572ba6f11ad5171fd5d59b0fbd (diff) | |
| download | linux-2b3f786408c5400705ed722ab2f3065e86272857.tar.gz | |
RISC-V: defconfig: Enable RISC-V SBI earlycon support
This patch enables RISC-V SBI earlycon support in default defconfig so that we can use "earlycon=sbi" in kernel parameters for early debug prints. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/configs')
| -rw-r--r-- | arch/riscv/configs/defconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index ef4f15df9adf..f399659d3b8d 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -46,6 +46,7 @@ CONFIG_INPUT_MOUSEDEV=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y CONFIG_HVC_RISCV_SBI=y # CONFIG_PTP_1588_CLOCK is not set CONFIG_DRM=y |