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| author | Marcelo Tosatti <marcelo.tosatti@cyclades.com> | 2006-01-23 13:57:06 -0200 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2006-02-07 21:28:37 +1100 |
| commit | 3ea4807de7b2c5c903380ba2c2e7150bee942f42 (patch) | |
| tree | 2e354cb0e3126ef47bf833bfe9e8eccd523091ad /arch/ppc | |
| parent | aee9f26542cc27a37d593f1790b84cd57801a7c7 (diff) | |
| download | linux-3ea4807de7b2c5c903380ba2c2e7150bee942f42.tar.gz | |
[PATCH] powerpc/8xx: last two 8MB D-TLB entries are incorrectly set
The last two 8MB TLB entries are being incorrectly set by initial_mmu on 8xx. The first entry is written with the same virtual/physical address, which renders it invalid: BDI>rms 792 0x00001e00 BDI>rms 824 1 BDI>rds 824 SPR 824 : 0xc08000c0 -1065353024 BDI>rds 825 SPR 825 : 0xc0800de0 -1065349664 BDI>rds 826 SPR 826 : 0x00000000 0 And the second entry, in addition, does not have its TLB index set correctly. Signed-off-by: Marcelo Tosatti <marcelo.tosatti@cyclades.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc')
| -rw-r--r-- | arch/ppc/kernel/head_8xx.S | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index 3e6ca7f5843f..c1e89ad0684d 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -810,13 +810,16 @@ initial_mmu: mtspr SPRN_MD_TWC, r9 li r11, MI_BOOTINIT /* Create RPN for address 0 */ addis r11, r11, 0x0080 /* Add 8M */ - mtspr SPRN_MD_RPN, r8 + mtspr SPRN_MD_RPN, r11 + + addi r10, r10, 0x0100 + mtspr SPRN_MD_CTR, r10 addis r8, r8, 0x0080 /* Add 8M */ mtspr SPRN_MD_EPN, r8 mtspr SPRN_MD_TWC, r9 addis r11, r11, 0x0080 /* Add 8M */ - mtspr SPRN_MD_RPN, r8 + mtspr SPRN_MD_RPN, r11 #endif /* Since the cache is enabled according to the information we |