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| author | Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> | 2013-11-27 10:07:53 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-01-22 20:19:01 +0100 |
| commit | 26ab96dfa9f98d74ef38efbe830d356547a292c1 (patch) | |
| tree | 3789a48dbf291811980cde03016eed2dfcde419a /arch/mips/kernel/traps.c | |
| parent | 0ce7d58ee0d814622bf7b4700925455dd4960ddd (diff) | |
| download | linux-26ab96dfa9f98d74ef38efbe830d356547a292c1.tar.gz | |
MIPS: Add support for interAptiv cores
The interAptiv is a power-efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The interAptiv combines a multi-threading pipeline with a coherence manager to deliver improved computational throughput and power efficiency. The interAptiv can contain one to four MIPS32R3 interAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6163/
Diffstat (limited to 'arch/mips/kernel/traps.c')
| -rw-r--r-- | arch/mips/kernel/traps.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 39370e1d4362..e0b499694d18 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1337,6 +1337,7 @@ static inline void parity_protection_init(void) case CPU_34K: case CPU_74K: case CPU_1004K: + case CPU_INTERAPTIV: case CPU_PROAPTIV: { #define ERRCTL_PE 0x80000000 |