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| author | Ralf Baechle <ralf@linux-mips.org> | 2007-11-08 18:02:29 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-11-15 23:21:49 +0000 |
| commit | f6771dbb27c704ce837ba3bb1dcaa53f48f76ea8 (patch) | |
| tree | efec5eacc34a9e412a193a79d575cbf3b90acf23 /arch/mips/kernel/proc.c | |
| parent | efb9ca08b5a2374b29938cdcab417ce4feb14b54 (diff) | |
| download | linux-f6771dbb27c704ce837ba3bb1dcaa53f48f76ea8.tar.gz | |
[MIPS] Fix shadow register support.
Shadow register support would not possibly have worked on multicore systems. The support code for it was also depending not on MIPS R2 but VSMP or SMTC kernels even though it makes perfect sense with UP kernels. SR sets are a scarce resource and the expected usage pattern is that users actually hardcode the register set numbers in their code. So fix the allocator by ditching it. Move the remaining CPU probe bits into the generic CPU probe. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/proc.c')
| -rw-r--r-- | arch/mips/kernel/proc.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index efd2d1314123..6e6e947cce1e 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -60,6 +60,8 @@ static int show_cpuinfo(struct seq_file *m, void *v) cpu_has_dsp ? " dsp" : "", cpu_has_mipsmt ? " mt" : "" ); + seq_printf(m, "shadow register sets\t: %d\n", + cpu_data[n].srsets); sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", cpu_has_vce ? "%u" : "not available"); |