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| author | 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> | 2020-07-22 13:21:19 +0800 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-07-24 11:13:57 +0200 |
| commit | 0d10d17bac3d5d4e97d6f008aa3c329a83d3b283 (patch) | |
| tree | 44ad6080d5d7b1e7aeea1af0218b23720bed60bb /arch/mips/kernel/cpu-probe.c | |
| parent | e8b9fc10f2615b9a525fce56981e40b489528355 (diff) | |
| download | linux-0d10d17bac3d5d4e97d6f008aa3c329a83d3b283.tar.gz | |
MIPS: X2000: Add X2000 system type.
1.Add "PRID_COMP_INGENIC_13" and "PRID_IMP_XBURST2" for X2000. 2.Add X2000 system type for cat /proc/cpuinfo to give out X2000. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/kernel/cpu-probe.c')
| -rw-r--r-- | arch/mips/kernel/cpu-probe.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index c231c1b67889..d9e8d39a7289 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -2110,6 +2110,8 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); switch (c->processor_id & PRID_IMP_MASK) { + + /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */ case PRID_IMP_XBURST_REV1: /* @@ -2148,12 +2150,20 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) break; } fallthrough; + + /* XBurst®1 with MXU2.0 SIMD ISA */ case PRID_IMP_XBURST_REV2: c->cputype = CPU_XBURST; c->writecombine = _CACHE_UNCACHED_ACCELERATED; __cpu_name[cpu] = "Ingenic XBurst"; break; + /* XBurst®2 with MXU2.1 SIMD ISA */ + case PRID_IMP_XBURST2: + c->cputype = CPU_XBURST; + __cpu_name[cpu] = "Ingenic XBurst II"; + break; + default: panic("Unknown Ingenic Processor ID!"); break; @@ -2299,6 +2309,7 @@ void cpu_probe(void) case PRID_COMP_LOONGSON: cpu_probe_loongson(c, cpu); break; + case PRID_COMP_INGENIC_13: case PRID_COMP_INGENIC_D0: case PRID_COMP_INGENIC_D1: case PRID_COMP_INGENIC_E1: |