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| author | Mike Frysinger <michael.frysinger@analog.com> | 2007-10-11 00:22:35 +0800 |
|---|---|---|
| committer | Bryan Wu <bryan.wu@analog.com> | 2007-10-11 00:22:35 +0800 |
| commit | 168f1212c098727f2509fe0f66bd30d7209a8159 (patch) | |
| tree | e749898e8ab56131a12d8fc489081321abb3ff2f /arch/blackfin/mach-bf561 | |
| parent | 27d875f2c134c4b26860ccdd03b4c52cce4efc2c (diff) | |
| download | linux-168f1212c098727f2509fe0f66bd30d7209a8159.tar.gz | |
Blackfin arch: rewrite our reboot code in C
rewrite our reboot code in C rather than assembly to be like other architectures and to allow board maintainers to define custom behavior Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/mach-bf561')
| -rw-r--r-- | arch/blackfin/mach-bf561/head.S | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S index 139f4cff801b..fd39891ae0fe 100644 --- a/arch/blackfin/mach-bf561/head.S +++ b/arch/blackfin/mach-bf561/head.S @@ -406,66 +406,6 @@ ENTRY(_start_dma_code) ENDPROC(_start_dma_code) #endif /* CONFIG_BFIN_KERNEL_CLOCK */ -ENTRY(_bfin_reset) - /* No more interrupts to be handled*/ - CLI R6; - SSYNC; - -#if defined(CONFIG_BFIN_SHARED_FLASH_ENET) - p0.h = hi(FIO_INEN); - p0.l = lo(FIO_INEN); - r0.l = ~(PF1 | PF0); - w[p0] = r0.l; - - p0.h = hi(FIO_DIR); - p0.l = lo(FIO_DIR); - r0.l = (PF1 | PF0); - w[p0] = r0.l; - - p0.h = hi(FIO_FLAG_C); - p0.l = lo(FIO_FLAG_C); - r0.l = (PF1 | PF0); - w[p0] = r0.l; -#endif - - /* Clear the IMASK register */ - p0.h = hi(IMASK); - p0.l = lo(IMASK); - r0 = 0x0; - [p0] = r0; - - /* Clear the ILAT register */ - p0.h = hi(ILAT); - p0.l = lo(ILAT); - r0 = [p0]; - [p0] = r0; - SSYNC; - - /* make sure SYSCR is set to use BMODE */ - P0.h = hi(SYSCR); - P0.l = lo(SYSCR); - R0.l = 0x20; /* on BF561, disable core b */ - W[P0] = R0.l; - SSYNC; - - /* issue a system soft reset */ - P1.h = hi(SWRST); - P1.l = lo(SWRST); - R1.l = 0x0007; - W[P1] = R1; - SSYNC; - - /* clear system soft reset */ - R0.l = 0x0000; - W[P0] = R0; - SSYNC; - - /* issue core reset */ - raise 1; - - RTS; -ENDPROC(_bfin_reset) - .data /* |