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| author | Douglas Anderson <dianders@chromium.org> | 2023-03-23 10:30:06 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2023-05-11 23:03:13 +0900 |
| commit | 0333177548fda2ca74c1e5075d78ae033829857f (patch) | |
| tree | 6f4b261c68b729dc7f157242aea44843b5f8399a /arch/arm64 | |
| parent | edbbd78148e7cfddd9e3022c508762eff95b8950 (diff) | |
| download | linux-0333177548fda2ca74c1e5075d78ae033829857f.tar.gz | |
arm64: dts: sc7280: Rename qspi data12 as data23
[ Upstream commit 14acf21c0d3f7b7298ffcd2e5b5db4a476ec6202 ]
There are 4 qspi data pins: data0, data1, data2, and data3. Currently
we have a shared pin state for data0 and data1 (2 lane config) and a
pin state for data2 and data3 (you'd enable both this and the 2 lane
state for 4 lanes). The second state is obviously misnamed. Fix it.
Fixes: 7720ea001b52 ("arm64: dts: qcom: sc7280: Add QSPI node")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323102605.2.I4043491bb24b1e92267c5033d76cdb0fe60934da@changeid
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 67e5f8d5f44f..0cdc579f26de 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4345,7 +4345,7 @@ function = "qspi_data"; }; - qspi_data12: qspi-data12-pins { + qspi_data23: qspi-data23-pins { pins = "gpio16", "gpio17"; function = "qspi_data"; }; |