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| author | James Clark <james.clark@arm.com> | 2022-09-01 14:26:57 +0100 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2022-09-22 15:06:02 +0100 |
| commit | cbb0c02caf4bd98b9e0cd6d7420734b8e9a35703 (patch) | |
| tree | 77998269afeffb99865493242d49ac78038eb8b0 /arch/arm64/include/uapi/asm | |
| parent | d813a19e7d2ec0c57477ee114f9b5e9a43cacb76 (diff) | |
| download | linux-cbb0c02caf4bd98b9e0cd6d7420734b8e9a35703.tar.gz | |
perf: arm64: Add SVE vector granule register to user regs
Dwarf based unwinding in a function that pushes SVE registers onto the stack requires the unwinder to know the length of the SVE register to calculate the stack offsets correctly. This was added to the Arm specific Dwarf spec as the VG pseudo register[1]. Add the vector length at position 46 if it's requested by userspace and SVE is supported. If it's not supported then fail to open the event. The vector length must be on each sample because it can be changed at runtime via a prctl or ptrace call. Also by adding it as a register rather than a separate attribute, minimal changes will be required in an unwinder that already indexes into the register list. [1]: https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst Reviewed-by: Mark Brown <broonie@kernel.org> Signed-off-by: James Clark <james.clark@arm.com> Link: https://lore.kernel.org/r/20220901132658.1024635-2-james.clark@arm.com Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/include/uapi/asm')
| -rw-r--r-- | arch/arm64/include/uapi/asm/perf_regs.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/include/uapi/asm/perf_regs.h b/arch/arm64/include/uapi/asm/perf_regs.h index d54daafa89e3..0d4b40c78e47 100644 --- a/arch/arm64/include/uapi/asm/perf_regs.h +++ b/arch/arm64/include/uapi/asm/perf_regs.h @@ -37,5 +37,12 @@ enum perf_event_arm_regs { PERF_REG_ARM64_SP, PERF_REG_ARM64_PC, PERF_REG_ARM64_MAX, + + /* Extended/pseudo registers */ + PERF_REG_ARM64_VG = 46, // SVE Vector Granule + PERF_REG_ARM64_EXTENDED_MAX }; + +#define PERF_REG_EXTENDED_MASK (1ULL << PERF_REG_ARM64_VG) + #endif /* _ASM_ARM64_PERF_REGS_H */ |