Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm

Pull second set of ARM changes from Russell King:
 "This is the remainder of the ARM changes for this merge window.
  Included in this request are:

   - fixes for kprobes for big-endian support
   - fix tracing in soft_restart
   - avoid phys address overflow in kdump code
   - fix reporting of read-only pmd bits in kernel page table dump
   - remove unnecessary (and possibly buggy) call to outer_flush_all()
   - fix a three sparse warnings (missing header file for function
     prototypes)
   - fix pj4 crashing single zImage (thanks to arm-soc merging changes
     which enables this with knowledge that the corresponding fix had
     not even been submitted for my tree before the merge window opened)
   - vfp macro cleanups
   - dump register state on undefined instruction userspace faults when
     debugging"

* 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
  Dump the registers on undefined instruction userspace faults
  ARM: 8018/1: Add {inc,dec}_preempt_count asm macros
  ARM: 8017/1: Move asm macro get_thread_info to asm/assembler.h
  ARM: 8016/1: Check cpu id in pj4_cp0_init.
  ARM: 8015/1: Add cpu_is_pj4 to distinguish PJ4 because it has some differences with V7
  ARM: add missing system_misc.h include to process.c
  ARM: 8009/1: dcscb.c: remove call to outer_flush_all()
  ARM: 8014/1: mm: fix reporting of read-only PMD bits
  ARM: 8012/1: kdump: Avoid overflow when converting pfn to physaddr
  ARM: 8010/1: avoid tracers in soft_restart
  ARM: kprobes-test: Workaround GAS .align bug
  ARM: kprobes-test: use <asm/opcodes.h> for Thumb instruction building
  ARM: kprobes-test: use <asm/opcodes.h> for ARM instruction building
  ARM: kprobes-test: use <asm/opcodes.h> for instruction accesses
  ARM: probes: fix instruction fetch order with <asm/opcodes.h>

1 files changed, 9 insertions, 4 deletions

diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
index 14d499688736..788495d35cf9 100644
--- a/arch/arm/mach-vexpress/dcscb.c
+++ b/arch/arm/mach-vexpress/dcscb.c
@@ -137,11 +137,16 @@ static void dcscb_power_down(void)
 		v7_exit_coherency_flush(all);
 
 		/*
-		 * This is a harmless no-op.  On platforms with a real
-		 * outer cache this might either be needed or not,
-		 * depending on where the outer cache sits.
+		 * A full outer cache flush could be needed at this point
+		 * on platforms with such a cache, depending on where the
+		 * outer cache sits. In some cases the notion of a "last
+		 * cluster standing" would need to be implemented if the
+		 * outer cache is shared across clusters. In any case, when
+		 * the outer cache needs flushing, there is no concurrent
+		 * access to the cache controller to worry about and no
+		 * special locking besides what is already provided by the
+		 * MCPM state machinery is needed.
 		 */
-		outer_flush_all();
 
 		/*
 		 * Disable cluster-level coherency by masking