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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-05-08 17:21:49 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-05-23 18:04:52 +0100 |
| commit | 5c61ddcfaf98fae4a0ac8077b06a07fb2ba6864a (patch) | |
| tree | f4e7e0865d40a1b17a0e684af27577987d56b76d /arch/arm/mach-mxs | |
| parent | d6e15d78537d2483bff05f0ee5b5cec6c4678fd5 (diff) | |
| download | linux-5c61ddcfaf98fae4a0ac8077b06a07fb2ba6864a.tar.gz | |
clocksource: convert MXS timrotv2 to 32-bit down counting clocksource
Convert the MXS timrotv2 32-bit down counting clocksource to the generic clocksource infrastructure. Cc: Sascha Hauer <kernel@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-mxs')
| -rw-r--r-- | arch/arm/mach-mxs/timer.c | 20 |
1 files changed, 7 insertions, 13 deletions
diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c index 13647f301860..cace0d2e5a55 100644 --- a/arch/arm/mach-mxs/timer.c +++ b/arch/arm/mach-mxs/timer.c @@ -101,11 +101,6 @@ static cycle_t timrotv1_get_cycles(struct clocksource *cs) & 0xffff0000) >> 16); } -static cycle_t timrotv2_get_cycles(struct clocksource *cs) -{ - return ~__raw_readl(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1)); -} - static int timrotv1_set_next_event(unsigned long evt, struct clock_event_device *dev) { @@ -230,8 +225,8 @@ static int __init mxs_clockevent_init(struct clk *timer_clk) static struct clocksource clocksource_mxs = { .name = "mxs_timer", .rating = 200, - .read = timrotv2_get_cycles, - .mask = CLOCKSOURCE_MASK(32), + .read = timrotv1_get_cycles, + .mask = CLOCKSOURCE_MASK(16), .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; @@ -239,12 +234,11 @@ static int __init mxs_clocksource_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); - if (timrot_is_v1()) { - clocksource_mxs.read = timrotv1_get_cycles; - clocksource_mxs.mask = CLOCKSOURCE_MASK(16); - } - - clocksource_register_hz(&clocksource_mxs, c); + if (timrot_is_v1()) + clocksource_register_hz(&clocksource_mxs, c); + else + clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1), + "mxs_timer", c, 200, 32, clocksource_mmio_readl_down); return 0; } |