diff options
| author | Roger Quadros <rogerq@ti.com> | 2016-03-01 15:44:47 +0200 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2016-03-01 09:58:09 -0800 |
| commit | 0c3e192ad2c36cfff33bacddc912ad885d2aae28 (patch) | |
| tree | 12f9dd0df75e5d47caff53904084a965c78aafff /arch/arm/boot | |
| parent | 5fcc673067a2b577d37f2c5c5439dbb177f7107e (diff) | |
| download | linux-0c3e192ad2c36cfff33bacddc912ad885d2aae28.tar.gz | |
ARM: dts: dm814x: dra62x: Fix NAND device nodes
Add compatible id, GPMC register resource and interrupt resource to NAND controller nodes. The GPMC node will provide an interrupt controller for the NAND IRQs. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/dm8148-evm.dts | 7 | ||||
| -rw-r--r-- | arch/arm/boot/dts/dm814x.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/dra62x-j5eco-evm.dts | 7 |
3 files changed, 14 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/dm8148-evm.dts b/arch/arm/boot/dts/dm8148-evm.dts index 862977f5a22a..be56c8fc323c 100644 --- a/arch/arm/boot/dts/dm8148-evm.dts +++ b/arch/arm/boot/dts/dm8148-evm.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "dm814x.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> / { model = "DM8148 EVM"; @@ -39,8 +40,12 @@ ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ nand@0,0 { - linux,mtd-name= "micron,mt29f2g16aadwp"; + compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + linux,mtd-name= "micron,mt29f2g16aadwp"; #address-cells = <1>; #size-cells = <1>; ti,nand-ecc-opt = "bch8"; diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index f752ac1d976a..4a6ce8c8bf8f 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -566,6 +566,8 @@ gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; }; }; }; diff --git a/arch/arm/boot/dts/dra62x-j5eco-evm.dts b/arch/arm/boot/dts/dra62x-j5eco-evm.dts index 3937a589d331..b0c8144a6e9e 100644 --- a/arch/arm/boot/dts/dra62x-j5eco-evm.dts +++ b/arch/arm/boot/dts/dra62x-j5eco-evm.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "dra62x.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> / { model = "DRA62x J5 Eco EVM"; @@ -39,8 +40,12 @@ ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ nand@0,0 { - linux,mtd-name= "micron,mt29f2g16aadwp"; + compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + linux,mtd-name= "micron,mt29f2g16aadwp"; #address-cells = <1>; #size-cells = <1>; ti,nand-ecc-opt = "bch8"; |