diff options
| author | Mans Rullgard <mans@mansr.com> | 2022-01-12 17:33:27 +0000 |
|---|---|---|
| committer | Maxime Ripard <maxime@cerno.tech> | 2022-01-24 09:11:26 +0100 |
| commit | b04138bfdebb33dfd265d1489a9f3d05f9bcc58e (patch) | |
| tree | 4234ff2fa4d31013f53132cc4ffa7e815f0708c3 /arch/arm/boot/dts/sunxi-h3-h5.dtsi | |
| parent | 0f960ce9debcdc3db43162a0d25f5875b3a509cf (diff) | |
| download | linux-b04138bfdebb33dfd265d1489a9f3d05f9bcc58e.tar.gz | |
ARM: dts: sunxi: h3/h5: add r_uart node
There is an additional UART in the PL I/O block. Add a node and pinmux for it. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20220112173327.26317-1-mans@mansr.com
Diffstat (limited to 'arch/arm/boot/dts/sunxi-h3-h5.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sunxi-h3-h5.dtsi | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 4aeca9e7e30d..d7e9f977f986 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -913,6 +913,19 @@ #size-cells = <0>; }; + r_uart: serial@1f02800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01f02800 0x400>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&r_ccu CLK_APB0_UART>; + resets = <&r_ccu RST_APB0_UART>; + pinctrl-names = "default"; + pinctrl-0 = <&r_uart_pins>; + status = "disabled"; + }; + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; @@ -939,6 +952,11 @@ pins = "PL10"; function = "s_pwm"; }; + + r_uart_pins: r-uart-pins { + pins = "PL2", "PL3"; + function = "s_uart"; + }; }; r_pwm: pwm@1f03800 { |