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| author | Olof Johansson <olof@lixom.net> | 2011-12-15 22:02:34 -0800 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2011-12-15 22:02:34 -0800 |
| commit | 02735a29d8ce882ec698803f064e17888874780c (patch) | |
| tree | 6a4afa3bc8b6d4334df24910a56f77adf126b0c7 /arch/arm/Kconfig | |
| parent | 8d685b7f4d9c9882442bf1b492558d5f17b694fa (diff) | |
| parent | 3d911ad22e8405c1a333a6812e405cb1a5ae9829 (diff) | |
| download | linux-02735a29d8ce882ec698803f064e17888874780c.tar.gz | |
Merge branch 'at91/defconfig' into next/cleanup
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 44789eff983f..e084b7e981e8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1231,7 +1231,7 @@ config ARM_ERRATA_742231 capabilities of the processor. config PL310_ERRATA_588369 - bool "Clean & Invalidate maintenance operations do not invalidate clean lines" + bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" depends on CACHE_L2X0 help The PL310 L2 cache controller implements three types of Clean & @@ -1256,7 +1256,7 @@ config ARM_ERRATA_720789 entries regardless of the ASID. config PL310_ERRATA_727915 - bool "Background Clean & Invalidate by Way operation can cause data corruption" + bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" depends on CACHE_L2X0 help PL310 implements the Clean & Invalidate by Way L2 cache maintenance @@ -1289,8 +1289,8 @@ config ARM_ERRATA_751472 operation is received by a CPU before the ICIALLUIS has completed, potentially leading to corrupted entries in the cache or TLB. -config ARM_ERRATA_753970 - bool "ARM errata: cache sync operation may be faulty" +config PL310_ERRATA_753970 + bool "PL310 errata: cache sync operation may be faulty" depends on CACHE_PL310 help This option enables the workaround for the 753970 PL310 (r3p0) erratum. @@ -1352,6 +1352,18 @@ config ARM_ERRATA_764369 relevant cache maintenance functions and sets a specific bit in the diagnostic control register of the SCU. +config PL310_ERRATA_769419 + bool "PL310 errata: no automatic Store Buffer drain" + depends on CACHE_L2X0 + help + On revisions of the PL310 prior to r3p2, the Store Buffer does + not automatically drain. This can cause normal, non-cacheable + writes to be retained when the memory system is idle, leading + to suboptimal I/O performance for drivers using coherent DMA. + This option adds a write barrier to the cpu_idle loop so that, + on systems with an outer cache, the store buffer is drained + explicitly. + endmenu source "arch/arm/common/Kconfig" |