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| author | Jordan Crouse <jcrouse@codeaurora.org> | 2018-07-24 10:33:30 -0600 |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2018-07-30 08:50:06 -0400 |
| commit | 50f8d21863b9b774b198e631d2b14878f6a54b5b (patch) | |
| tree | cea285532643cb33364c560cba90ecb624cf46d5 /Documentation/gpu | |
| parent | 43a56687d15db09f3cf7b9d53b182bdef86c17c0 (diff) | |
| download | linux-50f8d21863b9b774b198e631d2b14878f6a54b5b.tar.gz | |
drm/msm/adreno: Add a5xx specific registers for the GPU state
HLSQ, SP and TP registers are only accessible from a special aperture and to make matters worse the aperture is blocked from the CPU on targets that can support secure rendering. Luckily the GPU hardware has its own purpose built register dumper that can access the registers from the aperture. Add a5xx specific code to program the crashdumper and retrieve the wayward registers and dump them for the crash state. Also, remove a block of registers the regular CPU accessible list that aren't useful for debug which helps reduce the size of the crash state file by a goodly amount. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'Documentation/gpu')
| -rw-r--r-- | Documentation/gpu/msm-crash-dump.rst | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/gpu/msm-crash-dump.rst b/Documentation/gpu/msm-crash-dump.rst index 35e87004e006..7943f43f70d6 100644 --- a/Documentation/gpu/msm-crash-dump.rst +++ b/Documentation/gpu/msm-crash-dump.rst @@ -76,3 +76,7 @@ registers value Hexadecimal value of the register. + +registers-hlsq + (5xx only) Register values from the HLSQ aperture. + Same format as the register section. |