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| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2019-08-20 07:28:43 +0000 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2019-08-22 18:15:23 +0100 |
| commit | ee4ea764ea03253016034603cab352c0798ce173 (patch) | |
| tree | f47b1c63373b980859dded897ade44fe52ac0df1 /Documentation/devicetree/bindings/pci | |
| parent | 5ae6393e6d41c7cc38c1ce679bc91c475412c624 (diff) | |
| download | linux-ee4ea764ea03253016034603cab352c0798ce173.tar.gz | |
dt-bindings: PCI: designware: Remove the num-lanes from Required properties
The num-lanes is not a mandatory property, e.g. on FSL Layerscape SoCs, the PCIe link training is completed automatically based on the selected SerDes protocol, it does not need the num-lanes to set-up the link width. Currently it is both a Required and Optional property, let's remove it from the Required properties. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Diffstat (limited to 'Documentation/devicetree/bindings/pci')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/designware-pcie.txt | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index 5561a1c060d0..bd880df39a79 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -11,7 +11,6 @@ Required properties: the ATU address space. (The old way of getting the configuration address space from "ranges" is deprecated and should be avoided.) -- num-lanes: number of lanes to use RC mode: - #address-cells: set to <3> - #size-cells: set to <2> |