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| author | Geetha Sowjanya <geethasowjanya.akula@cavium.com> | 2017-06-23 19:04:36 +0530 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2017-06-23 17:58:04 +0100 |
| commit | f935448acf462c26142e8b04f1c8829b28d3b9d8 (patch) | |
| tree | 7516f4e4d39117e80be3b2859451725faded8271 /Documentation/arm64 | |
| parent | 99caf177f6fd3e67575f6ce05b36e8e041bcef60 (diff) | |
| download | linux-f935448acf462c26142e8b04f1c8829b28d3b9d8.tar.gz | |
iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126
Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq lines for gerror, eventq and cmdq-sync. New named irq "combined" is set as a errata workaround, which allows to share the irq line by register single irq handler for all the interrupts. Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Geetha sowjanya <gakula@caviumnetworks.com> [will: reworked irq equality checking and added SPI check] Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'Documentation/arm64')
| -rw-r--r-- | Documentation/arm64/silicon-errata.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index ef4e43590685..856479525776 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -63,6 +63,7 @@ stable kernels. | Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | | Cavium | ThunderX SMMUv2 | #27704 | N/A | | Cavium | ThunderX2 SMMUv3| #74 | N/A | +| Cavium | ThunderX2 SMMUv3| #126 | N/A | | | | | | | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | | | | | | |