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| author | Lijo Lazar <lijo.lazar@amd.com> | 2023-03-09 13:04:56 +0530 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-05-15 16:26:38 -0400 |
| commit | 38f1ab6435661e77cb33db7990e1bb7ca178cce2 (patch) | |
| tree | b41e1f27c637ef95264cc19d32f48ad13899a53f | |
| parent | 03959a5b4533363cce8879a5185180a2cd42e27f (diff) | |
| download | linux-38f1ab6435661e77cb33db7990e1bb7ca178cce2.tar.gz | |
drm/amdgpu: Add mode-2 reset in SMU v13.0.6
Modifications to mode-2 reset flow for SMU v13.0.6 ASICs. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/soc15.c | 9 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 16 |
2 files changed, 16 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 9fbfd0811d06..082c1e9308d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -556,6 +556,15 @@ soc15_asic_reset_method(struct amdgpu_device *adev) if (connected_to_cpu) return AMD_RESET_METHOD_MODE2; break; + case IP_VERSION(13, 0, 6): + /* Use gpu_recovery param to target a reset method. + * Enable triggering of GPU reset only if specified + * by module parameter. + */ + if (amdgpu_gpu_recovery == 4 || amdgpu_gpu_recovery == 5) + return AMD_RESET_METHOD_MODE2; + else + return AMD_RESET_METHOD_NONE; default: break; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 6dcafd04c98d..4b808c0addc2 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -2024,27 +2024,27 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table static int smu_v13_0_6_mode2_reset(struct smu_context *smu) { - u32 smu_version; int ret = 0, index; struct amdgpu_device *adev = smu->adev; int timeout = 10; - smu_cmn_get_smc_version(smu, NULL, &smu_version); - index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GfxDeviceDriverReset); mutex_lock(&smu->message_lock); + ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2); + /* This is similar to FLR, wait till max FLR timeout */ msleep(100); + dev_dbg(smu->adev->dev, "restore config space...\n"); /* Restore the config space saved during init */ amdgpu_device_load_pci_state(adev->pdev); dev_dbg(smu->adev->dev, "wait for reset ack\n"); - while (ret == -ETIME && timeout) { + do { ret = smu_cmn_wait_for_response(smu); /* Wait a bit more time for getting ACK */ if (ret == -ETIME) { @@ -2053,16 +2053,14 @@ static int smu_v13_0_6_mode2_reset(struct smu_context *smu) continue; } - if (ret != 1) { + if (ret) { dev_err(adev->dev, - "failed to send mode2 message \tparam: 0x%08x response %#x\n", + "failed to send mode2 message \tparam: 0x%08x error code %d\n", SMU_RESET_MODE_2, ret); goto out; } - } + } while (ret == -ETIME && timeout); - if (ret == 1) - ret = 0; out: mutex_unlock(&smu->message_lock); |