diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-03-31 08:51:45 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-03-31 08:51:45 -0700 |
| commit | d71e064449a704a026fa032ec852d532f08aefa1 (patch) | |
| tree | f282611ec43985fdbf988eede52a88e0465e78fc | |
| parent | 58233ccf94607c1df2c545b689c52c0b002f054e (diff) | |
| parent | ba15533275dd70238b523417d222d43fb40dac9d (diff) | |
| download | linux-d71e064449a704a026fa032ec852d532f08aefa1.tar.gz | |
Merge tag 'mips_5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Thomas Bogendoerfer: - loongson64 irq rework - dmi support loongson - replace setup_irq() by request_irq() - jazz cleanups - minor cleanups and fixes * tag 'mips_5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (44 commits) MIPS: ralink: mt7621: Fix soc_device introduction MIPS: Exclude more dsemul code when CONFIG_MIPS_FP_SUPPORT=n MIPS/tlbex: Fix LDDIR usage in setup_pw() for Loongson-3 MIPS: do not compile generic functions for CONFIG_CAVIUM_OCTEON_SOC MAINTAINERS: Update Loongson64 entry MIPS: Loongson64: Load built-in dtbs MIPS: Loongson64: Add generic dts dt-bindings: mips: Add loongson boards MIPS: Loongson64: Drop legacy IRQ code dt-bindings: interrupt-controller: Add Loongson-3 HTPIC irqchip: Add driver for Loongson-3 HyperTransport PIC controller dt-bindings: interrupt-controller: Add Loongson LIOINTC irqchip: loongson-liointc: Workaround LPC IRQ Errata irqchip: Add driver for Loongson I/O Local Interrupt Controller docs: mips: remove no longer needed au1xxx_ide.rst documentation MIPS: Alchemy: remove no longer used au1xxx_ide.h header ide: remove no longer used au1xxx-ide driver MIPS: Add support for Desktop Management Interface (DMI) firmware: dmi: Add macro SMBIOS_ENTRY_POINT_SCAN_START MIPS: ralink: mt7621: introduce 'soc_device' initialization ...
136 files changed, 1369 insertions, 1924 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml new file mode 100644 index 000000000000..c8861cbbb8b5 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Loongson-3 HyperTransport Interrupt Controller + +maintainers: + - Jiaxun Yang <jiaxun.yang@flygoat.com> + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +description: | + This interrupt controller is found in the Loongson-3 family of chips to transmit + interrupts from PCH PIC connected on HyperTransport bus. + +properties: + compatible: + const: loongson,htpic-1.0 + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 4 + description: | + Four parent interrupts that receive chained interrupts. + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + htintc: interrupt-controller@1fb000080 { + compatible = "loongson,htintc-1.0"; + reg = <0xfb000080 0x40>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&liointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; +... diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml new file mode 100644 index 000000000000..9c6b91fee477 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Loongson Local I/O Interrupt Controller + +maintainers: + - Jiaxun Yang <jiaxun.yang@flygoat.com> + +description: | + This interrupt controller is found in the Loongson-3 family of chips as the primary + package interrupt controller which can route local I/O interrupt to interrupt lines + of cores. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + oneOf: + - const: loongson,liointc-1.0 + - const: loongson,liointc-1.0a + + reg: + maxItems: 1 + + interrupt-controller: true + + interrupts: + description: + Interrupt source of the CPU interrupts. + minItems: 1 + maxItems: 4 + + interrupt-names: + description: List of names for the parent interrupts. + items: + - const: int0 + - const: int1 + - const: int2 + - const: int3 + minItems: 1 + maxItems: 4 + + '#interrupt-cells': + const: 2 + + 'loongson,parent_int_map': + description: | + This property points how the children interrupts will be mapped into CPU + interrupt lines. Each cell refers to a parent interrupt line from 0 to 3 + and each bit in the cell refers to a children interrupt fron 0 to 31. + If a CPU interrupt line didn't connected with liointc, then keep it's + cell with zero. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - items: + minItems: 4 + maxItems: 4 + + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - 'loongson,parent_int_map' + + +examples: + - | + iointc: interrupt-controller@3ff01400 { + compatible = "loongson,liointc-1.0"; + reg = <0x3ff01400 0x64>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>, <3>; + interrupt-names = "int0", "int1"; + + loongson,parent_int_map = <0xf0ffffff>, /* int0 */ + <0x0f000000>, /* int1 */ + <0x00000000>, /* int2 */ + <0x00000000>; /* int3 */ + + }; + +... diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml new file mode 100644 index 000000000000..74ed4e397a78 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/loongson/devices.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson based Platforms Device Tree Bindings + +maintainers: + - Jiaxun Yang <jiaxun.yang@flygoat.com> +description: | + Devices with a Loongson CPU shall have the following properties. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: Generic Loongson3 Quad Core + RS780E + items: + - const: loongson,loongson3-4core-rs780e + + - description: Generic Loongson3 Octa Core + RS780E + items: + - const: loongson,loongson3-8core-rs780e +... diff --git a/Documentation/mips/au1xxx_ide.rst b/Documentation/mips/au1xxx_ide.rst deleted file mode 100644 index 2f9c2cff6738..000000000000 --- a/Documentation/mips/au1xxx_ide.rst +++ /dev/null @@ -1,130 +0,0 @@ -.. include:: <isonum.txt> - -====================== -MIPS AU1XXX IDE driver -====================== - -Released 2005-07-15 - -About -===== - -This file describes the 'drivers/ide/au1xxx-ide.c', related files and the -services they provide. - -If you are short in patience and just want to know how to add your hard disc to -the white or black list, go to the 'ADD NEW HARD DISC TO WHITE OR BLACK LIST' -section. - - -License -======= - -:Copyright: |copy| 2003-2005 AMD, Personal Connectivity Solutions - -This program is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free Software -Foundation; either version 2 of the License, or (at your option) any later -version. - -THIS SOFTWARE IS PROVIDED ``AS IS`` AND ANY EXPRESS OR IMPLIED WARRANTIES, -INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND -FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR -BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - -You should have received a copy of the GNU General Public License along with -this program; if not, write to the Free Software Foundation, Inc., -675 Mass Ave, Cambridge, MA 02139, USA. - -Note: - for more information, please refer "AMD Alchemy Au1200/Au1550 IDE - Interface and Linux Device Driver" Application Note. - - -Files, Configs and Compatibility -================================ - -Two files are introduced: - - a) 'arch/mips/include/asm/mach-au1x00/au1xxx_ide.h' - contains : struct _auide_hwif - - - timing parameters for PIO mode 0/1/2/3/4 - - timing parameters for MWDMA 0/1/2 - - b) 'drivers/ide/mips/au1xxx-ide.c' - contains the functionality of the AU1XXX IDE driver - -Following extra configs variables are introduced: - - CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA - - enable the PIO+DBDMA mode - CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA - - enable the MWDMA mode - - -Supported IDE Modes -=================== - -The AU1XXX IDE driver supported all PIO modes - PIO mode 0/1/2/3/4 - and all -MWDMA modes - MWDMA 0/1/2 -. There is no support for SWDMA and UDMA mode. - -To change the PIO mode use the program hdparm with option -p, e.g. -'hdparm -p0 [device]' for PIO mode 0. To enable the MWDMA mode use the option --X, e.g. 'hdparm -X32 [device]' for MWDMA mode 0. - - -Performance Configurations -========================== - -If the used system doesn't need USB support enable the following kernel -configs:: - - CONFIG_IDE=y - CONFIG_BLK_DEV_IDE=y - CONFIG_IDE_GENERIC=y - CONFIG_BLK_DEV_IDEPCI=y - CONFIG_BLK_DEV_GENERIC=y - CONFIG_BLK_DEV_IDEDMA_PCI=y - CONFIG_BLK_DEV_IDE_AU1XXX=y - CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA=y - CONFIG_BLK_DEV_IDEDMA=y - -Also define 'IDE_AU1XXX_BURSTMODE' in 'drivers/ide/mips/au1xxx-ide.c' to enable -the burst support on DBDMA controller. - -If the used system need the USB support enable the following kernel configs for -high IDE to USB throughput. - -:: - - CONFIG_IDE_GENERIC=y - CONFIG_BLK_DEV_IDEPCI=y - CONFIG_BLK_DEV_GENERIC=y - CONFIG_BLK_DEV_IDEDMA_PCI=y - CONFIG_BLK_DEV_IDE_AU1XXX=y - CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA=y - CONFIG_BLK_DEV_IDEDMA=y - -Also undefine 'IDE_AU1XXX_BURSTMODE' in 'drivers/ide/mips/au1xxx-ide.c' to -disable the burst support on DBDMA controller. - - -Acknowledgments -=============== - -These drivers wouldn't have been done without the base of kernel 2.4.x AU1XXX -IDE driver from AMD. - -Additional input also from: -Matthias Lenk <matthias.lenk@amd.com> - -Happy hacking! - -Enrico Walther <enrico.walther@amd.com> diff --git a/Documentation/mips/index.rst b/Documentation/mips/index.rst index a93c2f65884c..d5ad8c00f0bd 100644 --- a/Documentation/mips/index.rst +++ b/Documentation/mips/index.rst @@ -10,8 +10,6 @@ MIPS-specific Documentation ingenic-tcu - au1xxx_ide - .. only:: subproject and html Indices diff --git a/MAINTAINERS b/MAINTAINERS index f114a90a23f8..c5ae60a85a22 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11202,6 +11202,7 @@ S: Maintained F: arch/mips/loongson64/ F: arch/mips/include/asm/mach-loongson64/ F: drivers/platform/mips/cpu_hwmon.c +F: drivers/irqchip/irq-loongson* F: drivers/*/*loongson3* F: drivers/*/*/*loongson3* diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 66e94278bd10..f8f3dbdd7ad5 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -486,9 +486,11 @@ config MACH_LOONGSON64 select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_ZBOOT - select LOONGSON_MC146818 select ZONE_DMA32 select NUMA + select COMMON_CLK + select USE_OF + select BUILTIN_DTB help This enables the support of Loongson-2/3 family of machines. @@ -973,6 +975,9 @@ config CAVIUM_OCTEON_SOC select SYS_HAS_EARLY_PRINTK select SYS_HAS_CPU_CAVIUM_OCTEON select HAVE_PCI + select HAVE_PLAT_DELAY + select HAVE_PLAT_FW_INIT_CMDLINE + select HAVE_PLAT_MEMCPY select ZONE_DMA32 select HOLES_IN_ZONE select GPIOLIB @@ -1229,6 +1234,15 @@ config GENERIC_ISA_DMA_SUPPORT_BROKEN bool select GENERIC_ISA_DMA +config HAVE_PLAT_DELAY + bool + +config HAVE_PLAT_FW_INIT_CMDLINE + bool + +config HAVE_PLAT_MEMCPY + bool + config ISA_DMA_API bool @@ -2676,7 +2690,7 @@ config NUMA Say Y to compile the kernel to support NUMA (Non-Uniform Memory Access). This option improves performance on systems with more than two nodes; on two node systems it is generally better to - leave it disabled; on single node systems disable this option + leave it disabled; on single node systems leave this option disabled. config SYS_SUPPORTS_NUMA @@ -2758,6 +2772,17 @@ config HW_PERF_EVENTS Enable hardware performance counter support for perf events. If disabled, perf events will use software events only. +config DMI + bool "Enable DMI scanning" + depends on MACH_LOONGSON64 + select DMI_SCAN_MACHINE_NON_EFI_FALLBACK + default y + help + Enabled scanning of DMI to identify machine quirks. Say Y + here unless you have verified that your setup is not + affected by entries in the DMI blacklist. Required by PNP + BIOS code. + config SMP bool "Multi-Processing support" depends on SYS_SUPPORTS_SMP @@ -3070,7 +3095,7 @@ endchoice choice prompt "Kernel command line type" if !CMDLINE_OVERRIDE default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \ - !MIPS_MALTA && \ + !MACH_LOONGSON64 && !MIPS_MALTA && \ !CAVIUM_OCTEON_SOC default MIPS_CMDLINE_FROM_BOOTLOADER diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index 3a21a6a18da7..d794ffb67412 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -72,13 +72,6 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = { .cpumask = cpu_possible_mask, }; -static struct irqaction au1x_rtcmatch2_irqaction = { - .handler = au1x_rtcmatch2_irq, - .flags = IRQF_TIMER, - .name = "timer", - .dev_id = &au1x_rtcmatch2_clockdev, -}; - static int __init alchemy_time_init(unsigned int m2int) { struct clock_event_device *cd = &au1x_rtcmatch2_clockdev; @@ -130,7 +123,9 @@ static int __init alchemy_time_init(unsigned int m2int) cd->min_delta_ns = clockevent_delta2ns(9, cd); cd->min_delta_ticks = 9; /* ~0.28ms */ clockevents_register_device(cd); - setup_irq(m2int, &au1x_rtcmatch2_irqaction); + if (request_irq(m2int, au1x_rtcmatch2_irq, IRQF_TIMER, "timer", + &au1x_rtcmatch2_clockdev)) + pr_err("Failed to register timer interrupt\n"); printk(KERN_INFO "Alchemy clocksource installed\n"); diff --git a/arch/mips/ar7/irq.c b/arch/mips/ar7/irq.c index 93a331fe0641..f0a7942d393e 100644 --- a/arch/mips/ar7/irq.c +++ b/arch/mips/ar7/irq.c @@ -83,12 +83,6 @@ static struct irq_chip ar7_sec_irq_type = { .irq_ack = ar7_ack_sec_irq, }; -static struct irqaction ar7_cascade_action = { - .handler = no_action, - .name = "AR7 cascade interrupt", - .flags = IRQF_NO_THREAD, -}; - static void __init ar7_irq_init(int base) { int i; @@ -116,8 +110,14 @@ static void __init ar7_irq_init(int base) handle_level_irq); } - setup_irq(2, &ar7_cascade_action); - setup_irq(ar7_irq_base, &ar7_cascade_action); + if (request_irq(2, no_action, IRQF_NO_THREAD, "AR7 cascade interrupt", + NULL)) + pr_err("Failed to request irq 2 (AR7 cascade interrupt)\n"); + if (request_irq(ar7_irq_base, no_action, IRQF_NO_THREAD, + "AR7 cascade interrupt", NULL)) { + pr_err("Failed to request irq %d (AR7 cascade interrupt)\n", + ar7_irq_base); + } set_c0_status(IE_IRQ0); } diff --git a/arch/mips/ath25/ar2315.c b/arch/mips/ath25/ar2315.c index 24f619199ee7..e7b53e3960c8 100644 --- a/arch/mips/ath25/ar2315.c +++ b/arch/mips/ath25/ar2315.c @@ -64,11 +64,6 @@ static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id) return IRQ_HANDLED; } -static struct irqaction ar2315_ahb_err_interrupt = { - .handler = ar2315_ahb_err_handler, - .name = "ar2315-ahb-error", -}; - static void ar2315_misc_irq_handler(struct irq_desc *desc) { u32 pending = ar2315_rst_reg_read(AR2315_ISR) & @@ -159,7 +154,9 @@ void __init ar2315_arch_init_irq(void) panic("Failed to add IRQ domain"); irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB); - setup_irq(irq, &ar2315_ahb_err_interrupt); + if (request_irq(irq, ar2315_ahb_err_handler, 0, "ar2315-ahb-error", + NULL)) + pr_err("Failed to register ar2315-ahb-error interrupt\n"); irq_set_chained_handler_and_data(AR2315_IRQ_MISC, ar2315_misc_irq_handler, domain); diff --git a/arch/mips/ath25/ar5312.c b/arch/mips/ath25/ar5312.c index 47f3e98974fc..42bf2afb4765 100644 --- a/arch/mips/ath25/ar5312.c +++ b/arch/mips/ath25/ar5312.c @@ -68,11 +68,6 @@ static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id) return IRQ_HANDLED; } -static struct irqaction ar5312_ahb_err_interrupt = { - .handler = ar5312_ahb_err_handler, - .name = "ar5312-ahb-error", -}; - static void ar5312_misc_irq_handler(struct irq_desc *desc) { u32 pending = ar5312_rst_reg_read(AR5312_ISR) & @@ -154,7 +149,9 @@ void __init ar5312_arch_init_irq(void) panic("Failed to add IRQ domain"); irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC); - setup_irq(irq, &ar5312_ahb_err_interrupt); + if (request_irq(irq, ar5312_ahb_err_handler, 0, "ar5312-ahb-error", + NULL)) + pr_err("Failed to register ar5312-ahb-error interrupt\n"); irq_set_chained_handler_and_data(AR5312_IRQ_MISC, ar5312_misc_irq_handler, domain); diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index 484ee28922a9..acb4fd647a30 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -15,7 +15,7 @@ #include <linux/memblock.h> #include <linux/err.h> #include <linux/clk.h> -#include <linux/clk-provider.h> +#include <linux/of_clk.h> #include <linux/of_fdt.h> #include <linux/irqchip.h> diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index ec694b9628c0..2548013442f6 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -399,26 +399,6 @@ static struct irq_chip bcm63xx_external_irq_chip = { .irq_set_type = bcm63xx_external_irq_set_type, }; -static struct irqaction cpu_ip2_cascade_action = { - .handler = no_action, - .name = "cascade_ip2", - .flags = IRQF_NO_THREAD, -}; - -#ifdef CONFIG_SMP -static struct irqaction cpu_ip3_cascade_action = { - .handler = no_action, - .name = "cascade_ip3", - .flags = IRQF_NO_THREAD, -}; -#endif - -static struct irqaction cpu_ext_cascade_action = { - .handler = no_action, - .name = "cascade_extirq", - .flags = IRQF_NO_THREAD, -}; - static void bcm63xx_init_irq(void) { int irq_bits; @@ -531,7 +511,7 @@ static void bcm63xx_init_irq(void) void __init arch_init_irq(void) { - int i; + int i, irq; bcm63xx_init_irq(); mips_cpu_irq_init(); @@ -544,14 +524,25 @@ void __init arch_init_irq(void) handle_edge_irq); if (!is_ext_irq_cascaded) { - for (i = 3; i < 3 + ext_irq_count; ++i) - setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action); + for (i = 3; i < 3 + ext_irq_count; ++i) { + irq = MIPS_CPU_IRQ_BASE + i; + if (request_irq(irq, no_action, IRQF_NO_THREAD, + "cascade_extirq", NULL)) { + pr_err("Failed to request irq %d (cascade_extirq)\n", + irq); + } + } } - setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action); + irq = MIPS_CPU_IRQ_BASE + 2; + if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade_ip2", NULL)) + pr_err("Failed to request irq %d (cascade_ip2)\n", irq); #ifdef CONFIG_SMP if (is_ext_irq_cascaded) { - setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action); + irq = MIPS_CPU_IRQ_BASE + 3; + if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade_ip3", + NULL)) + pr_err("Failed to request irq %d (cascade_ip3)\n", irq); bcm63xx_internal_irq_chip.irq_set_affinity = bcm63xx_internal_set_affinity; diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c index 2f81a94c71a6..19308df5f577 100644 --- a/arch/mips/bmips/setup.c +++ b/arch/mips/bmips/setup.c @@ -10,11 +10,11 @@ #include <linux/init.h> #include <linux/bitops.h> #include <linux/memblock.h> -#include <linux/clk-provider.h> #include <linux/ioport.h> #include <linux/kernel.h> #include <linux/io.h> #include <linux/of.h> +#include <linux/of_clk.h> #include <linux/of_fdt.h> #include <linux/of_platform.h> #include <linux/libfdt.h> diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index 1e79cab8e269..d429a69bfe30 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -4,6 +4,7 @@ subdir-y += cavium-octeon subdir-y += img subdir-y += ingenic subdir-y += lantiq +subdir-y += loongson subdir-y += mscc subdir-y += mti subdir-y += netlogic diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index c340f947baa0..db0ca250bd1a 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -4,6 +4,7 @@ #include "jz4780.dtsi" #include <dt-bindings/clock/ingenic,tcu.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/regulator/active-semi,8865-regulator.h> @@ -27,6 +28,17 @@ 0x30000000 0x30000000>; }; + gpio-keys { + compatible = "gpio-keys"; + + sw1 { + label = "ci20:sw1"; + linux,code = <KEY_F13>; + gpios = <&gpd 17 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + }; + leds { compatible = "gpio-leds"; @@ -58,10 +70,17 @@ eth0_power: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "eth0_power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; gpio = <&gpb 25 GPIO_ACTIVE_LOW>; enable-active-high; }; + ir: ir { + compatible = "gpio-ir-receiver"; + gpios = <&gpe 3 GPIO_ACTIVE_LOW>; + }; + wlan0_power: fixedregulator@1 { compatible = "regulator-fixed"; regulator-name = "wlan0_power"; diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile new file mode 100644 index 000000000000..56d379471262 --- /dev/null +++ b/arch/mips/boot/dts/loongson/Makefile @@ -0,0 +1,4 @@ +# SPDX_License_Identifier: GPL_2.0 +dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_rs780e.dtb loongson3_8core_rs780e.dtb + +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/mips/boot/dts/loongson/loongson3-package.dtsi b/arch/mips/boot/dts/loongson/loongson3-package.dtsi new file mode 100644 index 000000000000..5bb876a4de52 --- /dev/null +++ b/arch/mips/boot/dts/loongson/loongson3-package.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + package0: bus@1fe00000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x1fe00000 0 0x1fe00000 0x100000 + 0 0x3ff00000 0 0x3ff00000 0x100000 + /* 3A HT Config Space */ + 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000 + /* 3B HT Config Space */ + 0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000>; + + liointc: interrupt-controller@3ff01400 { + compatible = "loongson,liointc-1.0"; + reg = <0 0x3ff01400 0x64>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>, <3>; + interrupt-names = "int0", "int1"; + + loongson,parent_int_map = <0xf0ffffff>, /* int0 */ + <0x0f000000>, /* int1 */ + <0x00000000>, /* int2 */ + <0x00000000>; /* int3 */ + + }; + + cpu_uart0: serial@1fe001e0 { + compatible = "ns16550a"; + reg = <0 0x1fe001e0 0x8>; + clock-frequency = <33000000>; + interrupt-parent = <&liointc>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + no-loopback-test; + }; + + cpu_uart1: serial@1fe001e8 { + status = "disabled"; + compatible = "ns16550a"; + reg = <0 0x1fe001e8 0x8>; + clock-frequency = <33000000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&liointc>; + no-loopback-test; + }; + }; +}; diff --git a/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts new file mode 100644 index 000000000000..6b5694ca0f95 --- /dev/null +++ b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "loongson3-package.dtsi" +#include "rs780e-pch.dtsi" + +/ { + compatible = "loongson,loongson3-4core-rs780e"; +}; + +&package0 { + htpic: interrupt-controller@efdfb000080 { + compatible = "loongson,htpic-1.0"; + reg = <0xefd 0xfb000080 0x40>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&liointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts new file mode 100644 index 000000000000..ffefa2f829b0 --- /dev/null +++ b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "loongson3-package.dtsi" +#include "rs780e-pch.dtsi" + +/ { + compatible = "loongson,loongson3-8core-rs780e"; +}; + +&package0 { + htpic: interrupt-controller@1efdfb000080 { + compatible = "loongson,htpic-1.0"; + reg = <0x1efd 0xfb000080 0x40>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&liointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi new file mode 100644 index 000000000000..45c54d555fa4 --- /dev/null +++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + bus@10000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0x10000000 0 0x10000000 0 0x10000000 + 0 0x40000000 0 0x40000000 0 0x40000000 + 0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>; + + isa { + compatible = "isa"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0 0 0x1000>; + + rtc0: rtc@70 { + compatible = "motorola,mc146818"; + reg = <1 0x70 0x8>; + interrupts = <8>; + interrupt-parent = <&htpic>; + }; + }; + }; +}; diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 6bd1e97effdf..6501a842c41a 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -2199,6 +2199,9 @@ static int octeon_irq_cib_map(struct irq_domain *d, } cd = kzalloc(sizeof(*cd), GFP_KERNEL); + if (!cd) + return -ENOMEM; + cd->host_data = host_data; cd->bit = hw; diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c index 965c777d3561..ead5ae41378d 100644 --- a/arch/mips/cobalt/irq.c +++ b/arch/mips/cobalt/irq.c @@ -45,18 +45,20 @@ asmlinkage void plat_irq_dispatch(void) spurious_interrupt(); } -static struct irqaction cascade = { - .handler = no_action, - .name = "cascade", - .flags = IRQF_NO_THREAD, -}; - void __init arch_init_irq(void) { mips_cpu_irq_init(); gt641xx_irq_init(); init_i8259_irqs(); - setup_irq(GT641XX_CASCADE_IRQ, &cascade); - setup_irq(I8259_CASCADE_IRQ, &cascade); + if (request_irq(GT641XX_CASCADE_IRQ, no_action, IRQF_NO_THREAD, + "cascade", NULL)) { + pr_err("Failed to request irq %d (cascade)\n", + GT641XX_CASCADE_IRQ); + } + if (request_irq(I8259_CASCADE_IRQ, no_action, IRQF_NO_THREAD, + "cascade", NULL)) { + pr_err("Failed to request irq %d (cascade)\n", + I8259_CASCADE_IRQ); + } } diff --git a/arch/mips/configs/ar7_defconfig b/arch/mips/configs/ar7_defconfig index cef2754bd408..cf9c6329b807 100644 --- a/arch/mips/configs/ar7_defconfig +++ b/arch/mips/configs/ar7_defconfig @@ -21,7 +21,6 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y CONFIG_BSD_DISKLABEL=y -# CONFIG_IOSCHED_CFQ is not set CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y diff --git a/arch/mips/configs/ath25_defconfig b/arch/mips/configs/ath25_defconfig index c35add2fd716..7143441f5476 100644 --- a/arch/mips/configs/ath25_defconfig +++ b/arch/mips/configs/ath25_defconfig @@ -22,7 +22,6 @@ CONFIG_HZ_100=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_CFQ is not set # CONFIG_COMPACTION is not set CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/mips/configs/ath79_defconfig b/arch/mips/configs/ath79_defconfig index 4ffc59cab436..3d14d67dc746 100644 --- a/arch/mips/configs/ath79_defconfig +++ b/arch/mips/configs/ath79_defconfig @@ -23,7 +23,6 @@ CONFIG_PCI=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_CFQ is not set CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y diff --git a/arch/mips/configs/bcm63xx_defconfig b/arch/mips/configs/bcm63xx_defconfig index 54e2f9a659fb..861f680184b9 100644 --- a/arch/mips/configs/bcm63xx_defconfig +++ b/arch/mips/configs/bcm63xx_defconfig @@ -21,8 +21,6 @@ CONFIG_PCI=y CONFIG_PCCARD=y CONFIG_PCMCIA_BCM63XX=y # CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set CONFIG_NET=y CONFIG_UNIX=y CONFIG_INET=y diff --git a/arch/mips/configs/bmips_be_defconfig b/arch/mips/configs/bmips_be_defconfig index f669a40e085b..032bb51defe8 100644 --- a/arch/mips/configs/bmips_be_defconfig +++ b/arch/mips/configs/bmips_be_defconfig @@ -12,8 +12,6 @@ CONFIG_NR_CPUS=4 # CONFIG_SECCOMP is not set CONFIG_MIPS_O32_FP64_SUPPORT=y # CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set CONFIG_NET=y CONFIG_PACKET=y CONFIG_PACKET_DIAG=y diff --git a/arch/mips/configs/bmips_stb_defconfig b/arch/mips/configs/bmips_stb_defconfig index a0b775893dba..625bd2d7e685 100644 --- a/arch/mips/configs/bmips_stb_defconfig +++ b/arch/mips/configs/bmips_stb_defconfig @@ -21,8 +21,6 @@ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_BMIPS_CPUFREQ=y # CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set CONFIG_NET=y CONFIG_PACKET=y CONFIG_PACKET_DIAG=y diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig index be41df2a81fb..0db0088bbc1c 100644 --- a/arch/mips/configs/ci20_defconfig +++ b/arch/mips/configs/ci20_defconfig @@ -1,4 +1,5 @@ # CONFIG_LOCALVERSION_AUTO is not set +CONFIG_MODULES=y CONFIG_KERNEL_XZ=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y @@ -88,12 +89,14 @@ CONFIG_I2C_JZ4780=y CONFIG_SPI=y CONFIG_SPI_GPIO=y CONFIG_GPIO_SYSFS=y +CONFIG_KEYBOARD_GPIO=m # CONFIG_HWMON is not set CONFIG_WATCHDOG=y CONFIG_JZ4740_WDT=y CONFIG_REGULATOR=y CONFIG_REGULATOR_DEBUG=y CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ACT8865=y # CONFIG_VGA_CONSOLE is not set # CONFIG_HID is not set # CONFIG_USB_SUPPORT is not set @@ -166,3 +169,21 @@ CONFIG_STACKTRACE=y # CONFIG_FTRACE is not set CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="earlycon console=ttyS4,115200 clk_ignore_unused" +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_MTD=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=y +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LIRC=y +CONFIG_MEDIA_SUPPORT=m +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m diff --git a/arch/mips/configs/db1xxx_defconfig b/arch/mips/configs/db1xxx_defconfig index bc9b6ae046b2..e6f3e8e3da39 100644 --- a/arch/mips/configs/db1xxx_defconfig +++ b/arch/mips/configs/db1xxx_defconfig @@ -28,7 +28,6 @@ CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y CONFIG_FIRMWARE_MEMMAP=y CONFIG_BLK_DEV_BSGLIB=y CONFIG_PARTITION_ADVANCED=y -CONFIG_DEFAULT_NOOP=y CONFIG_CMA=y CONFIG_CMA_DEBUG=y CONFIG_NET=y diff --git a/arch/mips/configs/generic/board-ni169445.config b/arch/mips/configs/generic/board-ni169445.config index 1ed0d3e8715e..fc3580e4e6bc 100644 --- a/arch/mips/configs/generic/board-ni169445.config +++ b/arch/mips/configs/generic/board-ni169445.config @@ -19,7 +19,6 @@ CONFIG_MTD_NAND_ECC_SW_HAMMING=y CONFIG_MTD_NAND_ECC_SW_BCH=y CONFIG_MTD_RAW_NAND=y CONFIG_MTD_NAND_GPIO=y -CONFIG_MTD_NAND_IDS=y CONFIG_MTD_UBI=y CONFIG_MTD_UBI_BLOCK=y diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig index 328d4dfeb4cb..92085df3e367 100644 --- a/arch/mips/configs/jazz_defconfig +++ b/arch/mips/configs/jazz_defconfig @@ -1,15 +1,17 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT_VOLUNTARY=y CONFIG_BSD_PROCESS_ACCT=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MACH_JAZZ=y CONFIG_OLIVETTI_M700=y +CONFIG_MIPS_MAGNUM_4000=y +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y @@ -18,168 +20,17 @@ CONFIG_BINFMT_MISC=m CONFIG_NET=y CONFIG_PACKET=m CONFIG_UNIX=y -CONFIG_NET_KEY=m -CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_NET_IPIP=m -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_TCP_MD5SIG=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_TUNNEL=m -CONFIG_NETWORK_SECMARK=y -CONFIG_NETFILTER=y -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_SECMARK=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -CONFIG_DECNET_NF_GRABULATOR=m -CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_BROUTE=m -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m -CONFIG_BRIDGE_EBT_802_3=m -CONFIG_BRIDGE_EBT_AMONG=m -CONFIG_BRIDGE_EBT_ARP=m -CONFIG_BRIDGE_EBT_IP=m -CONFIG_BRIDGE_EBT_LIMIT=m -CONFIG_BRIDGE_EBT_MARK=m -CONFIG_BRIDGE_EBT_PKTTYPE=m -CONFIG_BRIDGE_EBT_STP=m -CONFIG_BRIDGE_EBT_VLAN=m -CONFIG_BRIDGE_EBT_ARPREPLY=m -CONFIG_BRIDGE_EBT_DNAT=m -CONFIG_BRIDGE_EBT_MARK_T=m -CONFIG_BRIDGE_EBT_REDIRECT=m -CONFIG_BRIDGE_EBT_SNAT=m -CONFIG_BRIDGE_EBT_LOG=m -CONFIG_BRIDGE=m -CONFIG_DECNET=m -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_CBQ=m -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_DSMARK=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m -CONFIG_HAMRADIO=y -CONFIG_AX25=m -CONFIG_NETROM=m -CONFIG_ROSE=m -CONFIG_MKISS=m -CONFIG_6PACK=m -CONFIG_BPQETHER=m -CONFIG_CONNECTOR=m CONFIG_PARPORT=m CONFIG_PARPORT_PC=m CONFIG_PARPORT_1284=y +CONFIG_DEVTMPFS=y CONFIG_BLK_DEV_FD=m -CONFIG_PARIDE=m -CONFIG_PARIDE_PD=m -CONFIG_PARIDE_PCD=m -CONFIG_PARIDE_PF=m -CONFIG_PARIDE_PT=m -CONFIG_PARIDE_PG=m -CONFIG_PARIDE_ATEN=m -CONFIG_PARIDE_BPCK=m -CONFIG_PARIDE_BPCK6=m -CONFIG_PARIDE_COMM=m -CONFIG_PARIDE_DSTR=m -CONFIG_PARIDE_FIT2=m -CONFIG_PARIDE_FIT3=m -CONFIG_PARIDE_EPAT=m -CONFIG_PARIDE_EPIA=m -CONFIG_PARIDE_FRIQ=m -CONFIG_PARIDE_FRPW=m -CONFIG_PARIDE_KBIC=m -CONFIG_PARIDE_KTTI=m -CONFIG_PARIDE_ON20=m -CONFIG_PARIDE_ON26=m CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_NBD=m @@ -194,26 +45,12 @@ CONFIG_BLK_DEV_SR=m CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SCSI_FC_ATTRS=y -CONFIG_SCSI_SAS_ATTRS=m CONFIG_ISCSI_TCP=m CONFIG_SCSI_PPA=m CONFIG_SCSI_IMM=m CONFIG_JAZZ_ESP=y -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID456=m -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m -CONFIG_BLK_DEV_DM=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_MIRROR=m -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m +CONFIG_ATA=y +CONFIG_PATA_LEGACY=y CONFIG_NETDEVICES=y CONFIG_BONDING=m CONFIG_DUMMY=m @@ -221,28 +58,18 @@ CONFIG_EQUALIZER=m CONFIG_TUN=m CONFIG_MIPS_JAZZ_SONIC=y CONFIG_NE2000=m -CONFIG_PHYLIB=m -CONFIG_CICADA_PHY=m -CONFIG_DAVICOM_PHY=m -CONFIG_LXT_PHY=m -CONFIG_MARVELL_PHY=m -CONFIG_QSEMI_PHY=m -CONFIG_SMSC_PHY=m -CONFIG_VITESSE_PHY=m -CONFIG_PLIP=m -CONFIG_INPUT_FF_MEMLESS=m CONFIG_SERIO_PARKBD=m CONFIG_SERIO_RAW=m CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_SERIAL_8250=m +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_DETECT_IRQ=y CONFIG_SERIAL_8250_RSA=y -CONFIG_PRINTER=m -CONFIG_PPDEV=m -# CONFIG_HW_RANDOM is not set -CONFIG_W1=m +CONFIG_FB=y +CONFIG_FB_G364=y +CONFIG_FRAMEBUFFER_CONSOLE=y # CONFIG_HWMON is not set CONFIG_EXT2_FS=m CONFIG_EXT3_FS=y @@ -263,78 +90,8 @@ CONFIG_VFAT_FS=m CONFIG_NTFS_FS=m CONFIG_PROC_KCORE=y CONFIG_TMPFS=y -CONFIG_ADFS_FS=m -CONFIG_AFFS_FS=m -CONFIG_HFS_FS=m -CONFIG_BEFS_FS=m -CONFIG_BFS_FS=m -CONFIG_EFS_FS=m -CONFIG_CRAMFS=m -CONFIG_VXFS_FS=m -CONFIG_MINIX_FS=m -CONFIG_HPFS_FS=m -CONFIG_QNX4FS_FS=m -CONFIG_ROMFS_FS=m -CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_NFS_FS=m CONFIG_NFSD=m CONFIG_NFSD_V3=y CONFIG_CIFS=m -CONFIG_CODA_FS=m -CONFIG_AFS_FS=m -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRC_CCITT=m diff --git a/arch/mips/configs/lasat_defconfig b/arch/mips/configs/lasat_defconfig index c66ca3785655..00cf461db971 100644 --- a/arch/mips/configs/lasat_defconfig +++ b/arch/mips/configs/lasat_defconfig @@ -16,8 +16,6 @@ CONFIG_HZ_1000=y # CONFIG_SECCOMP is not set CONFIG_PCI=y # CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig index f9f93427c9bd..8254d7d1396f 100644 --- a/arch/mips/configs/lemote2f_defconfig +++ b/arch/mips/configs/lemote2f_defconfig @@ -26,7 +26,7 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_IOSCHED_DEADLINE=m +CONFIG_MQ_IOSCHED_DEADLINE=m CONFIG_BINFMT_MISC=m CONFIG_NET=y CONFIG_PACKET=y diff --git a/arch/mips/configs/loongson3_defconfig b/arch/mips/configs/loongson3_defconfig index 360c6b2d397a..51675f5000d6 100644 --- a/arch/mips/configs/loongson3_defconfig +++ b/arch/mips/configs/loongson3_defconfig @@ -38,8 +38,9 @@ CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_PARTITION_ADVANCED=y -CONFIG_IOSCHED_DEADLINE=m -CONFIG_CFQ_GROUP_IOSCHED=y +CONFIG_MQ_IOSCHED_DEADLINE=m +CONFIG_IOSCHED_BFQ=y +CONFIG_BFQ_GROUP_IOSCHED=y CONFIG_BINFMT_MISC=m CONFIG_KSM=y CONFIG_NET=y diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig index 0fdc03fda12e..6ad1a2381226 100644 --- a/arch/mips/configs/msp71xx_defconfig +++ b/arch/mips/configs/msp71xx_defconfig @@ -14,8 +14,6 @@ CONFIG_PCI=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set CONFIG_NET=y CONFIG_UNIX=y CONFIG_XFRM_USER=y diff --git a/arch/mips/configs/pnx8335_stb225_defconfig b/arch/mips/configs/pnx8335_stb225_defconfig index 738ba3b1374b..d06db6b87959 100644 --- a/arch/mips/configs/pnx8335_stb225_defconfig +++ b/arch/mips/configs/pnx8335_stb225_defconfig @@ -14,8 +14,6 @@ CONFIG_HZ_128=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y diff --git a/arch/mips/configs/rb532_defconfig b/arch/mips/configs/rb532_defconfig index 5b947183852b..252d472387aa 100644 --- a/arch/mips/configs/rb532_defconfig +++ b/arch/mips/configs/rb532_defconfig @@ -23,7 +23,6 @@ CONFIG_MODULE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y CONFIG_MAC_PARTITION=y CONFIG_BSD_DISKLABEL=y -# CONFIG_IOSCHED_CFQ is not set CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y diff --git a/arch/mips/configs/rt305x_defconfig b/arch/mips/configs/rt305x_defconfig index 110948bc6b39..8c2ead53007a 100644 --- a/arch/mips/configs/rt305x_defconfig +++ b/arch/mips/configs/rt305x_defconfig @@ -21,7 +21,6 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y -# CONFIG_IOSCHED_CFQ is not set # CONFIG_COREDUMP is not set # CONFIG_COMPACTION is not set CONFIG_NET=y diff --git a/arch/mips/configs/xway_defconfig b/arch/mips/configs/xway_defconfig index 49b5ea6eff62..9abbc0debc2a 100644 --- a/arch/mips/configs/xway_defconfig +++ b/arch/mips/configs/xway_defconfig @@ -23,7 +23,6 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y -# CONFIG_IOSCHED_CFQ is not set # CONFIG_COREDUMP is not set # CONFIG_COMPACTION is not set CONFIG_NET=y diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c index 61a0bf13e308..d4e868b828e5 100644 --- a/arch/mips/dec/setup.c +++ b/arch/mips/dec/setup.c @@ -103,28 +103,8 @@ int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = { int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU); int *fpu_kstat_irq; -static struct irqaction ioirq = { - .handler = no_action, - .name = "cascade", - .flags = IRQF_NO_THREAD, -}; -static struct irqaction fpuirq = { - .handler = no_action, - .name = "fpu", - .flags = IRQF_NO_THREAD, -}; - -static struct irqaction busirq = { - .name = "bus error", - .flags = IRQF_NO_THREAD, -}; - -static struct irqaction haltirq = { - .handler = dec_intr_halt, - .name = "halt", - .flags = IRQF_NO_THREAD, -}; - +static irq_handler_t busirq_handler; +static unsigned int busirq_flags = IRQF_NO_THREAD; /* * Bus error (DBE/IBE exceptions and bus interrupts) handling setup. @@ -134,21 +114,21 @@ static void __init dec_be_init(void) switch (mips_machtype) { case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */ board_be_handler = dec_kn01_be_handler; - busirq.handler = dec_kn01_be_interrupt; - busirq.flags |= IRQF_SHARED; + busirq_handler = dec_kn01_be_interrupt; + busirq_flags |= IRQF_SHARED; dec_kn01_be_init(); break; case MACH_DS5000_1XX: /* DS5000/1xx 3min */ case MACH_DS5000_XX: /* DS5000/xx Maxine */ board_be_handler = dec_kn02xa_be_handler; - busirq.handler = dec_kn02xa_be_interrupt; + busirq_handler = dec_kn02xa_be_interrupt; dec_kn02xa_be_init(); break; case MACH_DS5000_200: /* DS5000/200 3max */ case MACH_DS5000_2X0: /* DS5000/240 3max+ */ case MACH_DS5900: /* DS5900 bigmax */ board_be_handler = dec_ecc_be_handler; - busirq.handler = dec_ecc_be_interrupt; + busirq_handler = dec_ecc_be_interrupt; dec_ecc_be_init(); break; } @@ -764,20 +744,29 @@ void __init arch_init_irq(void) int irq_fpu; irq_fpu = dec_interrupt[DEC_IRQ_FPU]; - setup_irq(irq_fpu, &fpuirq); + if (request_irq(irq_fpu, no_action, IRQF_NO_THREAD, "fpu", + NULL)) + pr_err("Failed to register fpu interrupt\n"); desc_fpu = irq_to_desc(irq_fpu); fpu_kstat_irq = this_cpu_ptr(desc_fpu->kstat_irqs); } - if (dec_interrupt[DEC_IRQ_CASCADE] >= 0) - setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq); - + if (dec_interrupt[DEC_IRQ_CASCADE] >= 0) { + if (request_irq(dec_interrupt[DEC_IRQ_CASCADE], no_action, + IRQF_NO_THREAD, "cascade", NULL)) + pr_err("Failed to register cascade interrupt\n"); + } /* Register the bus error interrupt. */ - if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq.handler) - setup_irq(dec_interrupt[DEC_IRQ_BUS], &busirq); - + if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq_handler) { + if (request_irq(dec_interrupt[DEC_IRQ_BUS], busirq_handler, + busirq_flags, "bus error", busirq_handler)) + pr_err("Failed to register bus error interrupt\n"); + } /* Register the HALT interrupt. */ - if (dec_interrupt[DEC_IRQ_HALT] >= 0) - setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq); + if (dec_interrupt[DEC_IRQ_HALT] >= 0) { + if (request_irq(dec_interrupt[DEC_IRQ_HALT], dec_intr_halt, + IRQF_NO_THREAD, "halt", NULL)) + pr_err("Failed to register halt interrupt\n"); + } } asmlinkage unsigned int dec_irq_dispatch(unsigned int irq) diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c index 09427a49e7ae..4aebf559be2e 100644 --- a/arch/mips/emma/markeins/irq.c +++ b/arch/mips/emma/markeins/irq.c @@ -153,14 +153,6 @@ void emma2rh_gpio_irq_init(void) handle_edge_irq, "edge"); } -static struct irqaction irq_cascade = { - .handler = no_action, - .flags = IRQF_NO_THREAD, - .name = "cascade", - .dev_id = NULL, - .next = NULL, -}; - /* * the first level int-handler will jump here if it is a emma2rh irq */ @@ -236,6 +228,7 @@ void emma2rh_irq_dispatch(void) void __init arch_init_irq(void) { u32 reg; + int irq; /* by default, interrupts are disabled. */ emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0); @@ -272,9 +265,15 @@ void __init arch_init_irq(void) mips_cpu_irq_init(); /* setup cascade interrupts */ - setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade); - setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade); - setup_irq(MIPS_CPU_IRQ_BASE + 2, &irq_cascade); + irq = EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE; + if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL)) + pr_err("Failed to request irq %d (cascade)\n", irq); + irq = EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE; + if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL)) + pr_err("Failed to request irq %d (cascade)\n", irq); + irq = MIPS_CPU_IRQ_BASE + 2; + if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL)) + pr_err("Failed to request irq %d (cascade)\n", irq); } asmlinkage void plat_irq_dispatch(void) diff --git a/arch/mips/fw/lib/cmdline.c b/arch/mips/fw/lib/cmdline.c index 6ecda64ad184..f24cbb4a39b5 100644 --- a/arch/mips/fw/lib/cmdline.c +++ b/arch/mips/fw/lib/cmdline.c @@ -16,6 +16,7 @@ int fw_argc; int *_fw_argv; int *_fw_envp; +#ifndef CONFIG_HAVE_PLAT_FW_INIT_CMDLINE void __init fw_init_cmdline(void) { int i; @@ -41,6 +42,7 @@ void __init fw_init_cmdline(void) strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE); } } +#endif char * __init fw_getcmdline(void) { diff --git a/arch/mips/generic/init.c b/arch/mips/generic/init.c index 1de215b283d6..805d0135a9f4 100644 --- a/arch/mips/generic/init.c +++ b/arch/mips/generic/init.c @@ -5,10 +5,10 @@ */ #include <linux/clk.h> -#include <linux/clk-provider.h> #include <linux/clocksource.h> #include <linux/init.h> #include <linux/irqchip.h> +#include <linux/of_clk.h> #include <linux/of_fdt.h> #include <asm/bootinfo.h> diff --git a/arch/mips/include/asm/dmi.h b/arch/mips/include/asm/dmi.h new file mode 100644 index 000000000000..27415a288adf --- /dev/null +++ b/arch/mips/include/asm/dmi.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_DMI_H +#define _ASM_DMI_H + +#include <linux/io.h> +#include <linux/memblock.h> + +#define dmi_early_remap(x, l) ioremap_cache(x, l) +#define dmi_early_unmap(x, l) iounmap(x) +#define dmi_remap(x, l) ioremap_cache(x, l) +#define dmi_unmap(x) iounmap(x) + +/* MIPS initialize DMI scan before SLAB is ready, so we use memblock here */ +#define dmi_alloc(l) memblock_alloc_low(l, PAGE_SIZE) + +#if defined(CONFIG_MACH_LOONGSON64) +#define SMBIOS_ENTRY_POINT_SCAN_START 0xFFFE000 +#endif + +#endif /* _ASM_DMI_H */ diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h index f8f44b1a6cbb..5aa29ced6970 100644 --- a/arch/mips/include/asm/elf.h +++ b/arch/mips/include/asm/elf.h @@ -445,6 +445,9 @@ extern unsigned int elf_hwcap; #define ELF_PLATFORM __elf_platform extern const char *__elf_platform; +#define ELF_BASE_PLATFORM __elf_base_platform +extern const char *__elf_base_platform; + /* * See comments in asm-alpha/elf.h, this is the same thing * on the MIPS. diff --git a/arch/mips/include/asm/i8259.h b/arch/mips/include/asm/i8259.h index 97a5e41ed1ab..a54b9649de22 100644 --- a/arch/mips/include/asm/i8259.h +++ b/arch/mips/include/asm/i8259.h @@ -36,6 +36,7 @@ extern raw_spinlock_t i8259A_lock; extern void make_8259A_irq(unsigned int irq); extern void init_i8259_irqs(void); +extern struct irq_domain *__init_i8259_irqs(struct device_node *node); /** * i8159_set_poll() - Override the i8259 polling function diff --git a/arch/mips/include/asm/mach-ar7/irq.h b/arch/mips/include/asm/mach-ar7/irq.h index 7ad10e379e2b..46bb730ea970 100644 --- a/arch/mips/include/asm/mach-ar7/irq.h +++ b/arch/mips/include/asm/mach-ar7/irq.h @@ -11,6 +11,6 @@ #define NR_IRQS 256 -#include_next <irq.h> +#include <asm/mach-generic/irq.h> #endif /* __ASM_AR7_IRQ_H */ diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h index 2df1abf9e5af..882534be0715 100644 --- a/arch/mips/include/asm/mach-ath79/irq.h +++ b/arch/mips/include/asm/mach-ath79/irq.h @@ -27,6 +27,6 @@ #define ATH79_IP3_IRQ_COUNT 3 #define ATH79_IP3_IRQ(_x) (ATH79_IP3_IRQ_BASE + (_x)) -#include_next <irq.h> +#include <asm/mach-generic/irq.h> #endif /* __ASM_MACH_ATH79_IRQ_H */ diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h deleted file mode 100644 index bb91b8923a49..000000000000 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * include/asm-mips/mach-au1x00/au1xxx_ide.h version 01.30.00 Aug. 02 2005 - * - * BRIEF MODULE DESCRIPTION - * AMD Alchemy Au1xxx IDE interface routines over the Static Bus - * - * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your option) any later - * version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE - * Interface and Linux Device Driver" Application Note. - */ - -#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA -#define DMA_WAIT_TIMEOUT 100 -#define NUM_DESCRIPTORS PRD_ENTRIES -#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */ -#define NUM_DESCRIPTORS 2 -#endif - -#ifndef AU1XXX_ATA_RQSIZE -#define AU1XXX_ATA_RQSIZE 128 -#endif - -/* Disable Burstable-Support for DBDMA */ -#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON -#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0 -#endif - -typedef struct { - u32 tx_dev_id, rx_dev_id, target_dev_id; - u32 tx_chan, rx_chan; - void *tx_desc_head, *rx_desc_head; - ide_hwif_t *hwif; -#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA - ide_drive_t *drive; - struct dbdma_cmd *dma_table_cpu; - dma_addr_t dma_table_dma; -#endif - int irq; - u32 regbase; - int ddma_id; -} _auide_hwif; - -/******************************************************************************/ -/* PIO Mode timing calculation : */ -/* */ -/* Static Bus Spec ATA Spec */ -/* Tcsoe = t1 */ -/* Toecs = t9 */ -/* Twcs = t9 */ -/* Tcsh = t2i | t2 */ -/* Tcsoff = t2i | t2 */ -/* Twp = t2 */ -/* Tcsw = t1 */ -/* Tpm = 0 */ -/* Ta = t1+t2 */ -/******************************************************************************/ - -#define TCSOE_MASK (0x07 << 29) -#define TOECS_MASK (0x07 << 26) -#define TWCS_MASK (0x07 << 28) -#define TCSH_MASK (0x0F << 24) -#define TCSOFF_MASK (0x07 << 20) -#define TWP_MASK (0x3F << 14) -#define TCSW_MASK (0x0F << 10) -#define TPM_MASK (0x0F << 6) -#define TA_MASK (0x3F << 0) -#define TS_MASK (1 << 8) - -/* Timing parameters PIO mode 0 */ -#define SBC_IDE_PIO0_TCSOE (0x04 << 29) -#define SBC_IDE_PIO0_TOECS (0x01 << 26) -#define SBC_IDE_PIO0_TWCS (0x02 << 28) -#define SBC_IDE_PIO0_TCSH (0x08 << 24) -#define SBC_IDE_PIO0_TCSOFF (0x07 << 20) -#define SBC_IDE_PIO0_TWP (0x10 << 14) -#define SBC_IDE_PIO0_TCSW (0x04 << 10) -#define SBC_IDE_PIO0_TPM (0x00 << 6) -#define SBC_IDE_PIO0_TA (0x15 << 0) -/* Timing parameters PIO mode 1 */ -#define SBC_IDE_PIO1_TCSOE (0x03 << 29) -#define SBC_IDE_PIO1_TOECS (0x01 << 26) -#define SBC_IDE_PIO1_TWCS (0x01 << 28) -#define SBC_IDE_PIO1_TCSH (0x06 << 24) -#define SBC_IDE_PIO1_TCSOFF (0x06 << 20) -#define SBC_IDE_PIO1_TWP (0x08 << 14) -#define SBC_IDE_PIO1_TCSW (0x03 << 10) -#define SBC_IDE_PIO1_TPM (0x00 << 6) -#define SBC_IDE_PIO1_TA (0x0B << 0) -/* Timing parameters PIO mode 2 */ -#define SBC_IDE_PIO2_TCSOE (0x05 << 29) -#define SBC_IDE_PIO2_TOECS (0x01 << 26) -#define SBC_IDE_PIO2_TWCS (0x01 << 28) -#define SBC_IDE_PIO2_TCSH (0x07 << 24) -#define SBC_IDE_PIO2_TCSOFF (0x07 << 20) -#define SBC_IDE_PIO2_TWP (0x1F << 14) -#define SBC_IDE_PIO2_TCSW (0x05 << 10) -#define SBC_IDE_PIO2_TPM (0x00 << 6) -#define SBC_IDE_PIO2_TA (0x22 << 0) -/* Timing parameters PIO mode 3 */ -#define SBC_IDE_PIO3_TCSOE (0x05 << 29) -#define SBC_IDE_PIO3_TOECS (0x01 << 26) -#define SBC_IDE_PIO3_TWCS (0x01 << 28) -#define SBC_IDE_PIO3_TCSH (0x0D << 24) -#define SBC_IDE_PIO3_TCSOFF (0x0D << 20) -#define SBC_IDE_PIO3_TWP (0x15 << 14) -#define SBC_IDE_PIO3_TCSW (0x05 << 10) -#define SBC_IDE_PIO3_TPM (0x00 << 6) -#define SBC_IDE_PIO3_TA (0x1A << 0) -/* Timing parameters PIO mode 4 */ -#define SBC_IDE_PIO4_TCSOE (0x04 << 29) -#define SBC_IDE_PIO4_TOECS (0x01 << 26) -#define SBC_IDE_PIO4_TWCS (0x01 << 28) -#define SBC_IDE_PIO4_TCSH (0x04 << 24) -#define SBC_IDE_PIO4_TCSOFF (0x04 << 20) -#define SBC_IDE_PIO4_TWP (0x0D << 14) -#define SBC_IDE_PIO4_TCSW (0x03 << 10) -#define SBC_IDE_PIO4_TPM (0x00 << 6) -#define SBC_IDE_PIO4_TA (0x12 << 0) -/* Timing parameters MDMA mode 0 */ -#define SBC_IDE_MDMA0_TCSOE (0x03 << 29) -#define SBC_IDE_MDMA0_TOECS (0x01 << 26) -#define SBC_IDE_MDMA0_TWCS (0x01 << 28) -#define SBC_IDE_MDMA0_TCSH (0x07 << 24) -#define SBC_IDE_MDMA0_TCSOFF (0x07 << 20) -#define SBC_IDE_MDMA0_TWP (0x0C << 14) -#define SBC_IDE_MDMA0_TCSW (0x03 << 10) -#define SBC_IDE_MDMA0_TPM (0x00 << 6) -#define SBC_IDE_MDMA0_TA (0x0F << 0) -/* Timing parameters MDMA mode 1 */ -#define SBC_IDE_MDMA1_TCSOE (0x05 << 29) -#define SBC_IDE_MDMA1_TOECS (0x01 << 26) -#define SBC_IDE_MDMA1_TWCS (0x01 << 28) -#define SBC_IDE_MDMA1_TCSH (0x05 << 24) -#define SBC_IDE_MDMA1_TCSOFF (0x05 << 20) -#define SBC_IDE_MDMA1_TWP (0x0F << 14) -#define SBC_IDE_MDMA1_TCSW (0x05 << 10) -#define SBC_IDE_MDMA1_TPM (0x00 << 6) -#define SBC_IDE_MDMA1_TA (0x15 << 0) -/* Timing parameters MDMA mode 2 */ -#define SBC_IDE_MDMA2_TCSOE (0x04 << 29) -#define SBC_IDE_MDMA2_TOECS (0x01 << 26) -#define SBC_IDE_MDMA2_TWCS (0x01 << 28) -#define SBC_IDE_MDMA2_TCSH (0x04 << 24) -#define SBC_IDE_MDMA2_TCSOFF (0x04 << 20) -#define SBC_IDE_MDMA2_TWP (0x0D << 14) -#define SBC_IDE_MDMA2_TCSW (0x04 << 10) -#define SBC_IDE_MDMA2_TPM (0x00 << 6) -#define SBC_IDE_MDMA2_TA (0x12 << 0) - -#define SBC_IDE_TIMING(mode) \ - (SBC_IDE_##mode##_TWCS | \ - SBC_IDE_##mode##_TCSH | \ - SBC_IDE_##mode##_TCSOFF | \ - SBC_IDE_##mode##_TWP | \ - SBC_IDE_##mode##_TCSW | \ - SBC_IDE_##mode##_TPM | \ - SBC_IDE_##mode##_TA) diff --git a/arch/mips/include/asm/mach-emma2rh/irq.h b/arch/mips/include/asm/mach-emma2rh/irq.h index 2f7155dade29..d32736736bb3 100644 --- a/arch/mips/include/asm/mach-emma2rh/irq.h +++ b/arch/mips/include/asm/mach-emma2rh/irq.h @@ -10,6 +10,6 @@ #define NR_IRQS 256 -#include_next <irq.h> +#include <asm/mach-generic/irq.h> #endif /* __ASM_MACH_EMMA2RH_IRQ_H */ diff --git a/arch/mips/include/asm/mach-ip27/irq.h b/arch/mips/include/asm/mach-ip27/irq.h index fd91c58aaf7d..f45d7999fd73 100644 --- a/arch/mips/include/asm/mach-ip27/irq.h +++ b/arch/mips/include/asm/mach-ip27/irq.h @@ -12,7 +12,7 @@ #define NR_IRQS 256 -#include_next <irq.h> +#include <asm/mach-generic/irq.h> #define IP27_HUB_PEND0_IRQ (MIPS_CPU_IRQ_BASE + 2) #define IP27_HUB_PEND1_IRQ (MIPS_CPU_IRQ_BASE + 3) diff --git a/arch/mips/include/asm/mach-ip30/irq.h b/arch/mips/include/asm/mach-ip30/irq.h index e5c3dd965266..27ba899c95be 100644 --- a/arch/mips/include/asm/mach-ip30/irq.h +++ b/arch/mips/include/asm/mach-ip30/irq.h @@ -76,7 +76,7 @@ extern void __init ip30_install_ipi(void); */ #define IP30_POWER_IRQ HEART_L2_INT_POWER_BTN -#include_next <irq.h> +#include <asm/mach-generic/irq.h> #define IP30_HEART_L0_IRQ (MIPS_CPU_IRQ_BASE + 2) #define IP30_HEART_L1_IRQ (MIPS_CPU_IRQ_BASE + 3) diff --git a/arch/mips/include/asm/mach-lantiq/falcon/irq.h b/arch/mips/include/asm/mach-lantiq/falcon/irq.h index 91d2bc03c9fa..c14312fb0574 100644 --- a/arch/mips/include/asm/mach-lantiq/falcon/irq.h +++ b/arch/mips/include/asm/mach-lantiq/falcon/irq.h @@ -11,6 +11,6 @@ #define NR_IRQS 328 -#include_next <irq.h> +#include <asm/mach-generic/irq.h> #endif diff --git a/arch/mips/include/asm/mach-lantiq/xway/irq.h b/arch/mips/include/asm/mach-lantiq/xway/irq.h index 76ebbf6c50ef..2980e7771f83 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/irq.h +++ b/arch/mips/include/asm/mach-lantiq/xway/irq.h @@ -11,6 +11,6 @@ #define NR_IRQS 256 -#include_next <irq.h> +#include <asm/mach-generic/irq.h> #endif diff --git a/arch/mips/include/asm/mach-lasat/irq.h b/arch/mips/include/asm/mach-lasat/irq.h index d79cbe075084..e8994921779e 100644 --- a/arch/mips/include/asm/mach-lasat/irq.h +++ b/arch/mips/include/asm/mach-lasat/irq.h @@ -9,6 +9,6 @@ #define NR_IRQS 24 -#include_next <irq.h> +#include <asm/mach-generic/irq.h> #endif /* _ASM_MACH_LASAT_IRQ_H */ diff --git a/arch/mips/include/asm/mach-loongson64/boot_param.h b/arch/mips/include/asm/mach-loongson64/boot_param.h index 8c286bedff3e..2ed483e32d8c 100644 --- a/arch/mips/include/asm/mach-loongson64/boot_param.h +++ b/arch/mips/include/asm/mach-loongson64/boot_param.h @@ -2,6 +2,8 @@ #ifndef __ASM_MACH_LOONGSON64_BOOT_PARAM_H_ #define __ASM_MACH_LOONGSON64_BOOT_PARAM_H_ +#include <linux/types.h> + #define SYSTEM_RAM_LOW 1 #define SYSTEM_RAM_HIGH 2 #define SYSTEM_RAM_RESERVED 3 diff --git a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h new file mode 100644 index 000000000000..853c6d80887b --- /dev/null +++ b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2019 Jiaxun Yang <jiaxun.yang@flygoat.com> + * + * Built-in Generic dtbs for MACH_LOONGSON64 + */ + +#ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_ +#define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_ + +extern u32 __dtb_loongson3_4core_rs780e_begin[]; +extern u32 __dtb_loongson3_8core_rs780e_begin[]; +#endif diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index 73a89913dc38..d41dc4a76e6d 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -7,34 +7,6 @@ /* cpu core interrupt numbers */ #define MIPS_CPU_IRQ_BASE 56 -#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */ -#define LOONGSON_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 3) /* CASCADE */ -#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */ +#include <asm/mach-generic/irq.h> -#define LOONGSON_HT1_CFG_BASE loongson_sysconf.ht_control_base -#define LOONGSON_HT1_INT_VECTOR_BASE (LOONGSON_HT1_CFG_BASE + 0x80) -#define LOONGSON_HT1_INT_EN_BASE (LOONGSON_HT1_CFG_BASE + 0xa0) -#define LOONGSON_HT1_INT_VECTOR(n) \ - LOONGSON3_REG32(LOONGSON_HT1_INT_VECTOR_BASE, 4 * (n)) -#define LOONGSON_HT1_INTN_EN(n) \ - LOONGSON3_REG32(LOONGSON_HT1_INT_EN_BASE, 4 * (n)) - -#define LOONGSON_INT_ROUTER_OFFSET 0x1400 -#define LOONGSON_INT_ROUTER_INTEN \ - LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x24) -#define LOONGSON_INT_ROUTER_INTENSET \ - LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x28) -#define LOONGSON_INT_ROUTER_INTENCLR \ - LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x2c) -#define LOONGSON_INT_ROUTER_ENTRY(n) \ - LOONGSON3_REG8(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + n) -#define LOONGSON_INT_ROUTER_LPC LOONGSON_INT_ROUTER_ENTRY(0x0a) -#define LOONGSON_INT_ROUTER_HT1(n) LOONGSON_INT_ROUTER_ENTRY(n + 0x18) - -#define LOONGSON_INT_COREx_INTy(x, y) (1<<(x) | 1<<(y+4)) /* route to int y of core x */ - -extern void fixup_irqs(void); -extern void loongson3_ipi_interrupt(struct pt_regs *regs); - -#include_next <irq.h> #endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */ diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h b/arch/mips/include/asm/mach-loongson64/loongson.h index a8fce112a9b0..fde1b75c45ea 100644 --- a/arch/mips/include/asm/mach-loongson64/loongson.h +++ b/arch/mips/include/asm/mach-loongson64/loongson.h @@ -25,6 +25,7 @@ extern const struct plat_smp_ops loongson3_smp_ops; /* loongson-specific command line, env and memory initialization */ extern void __init prom_init_memory(void); extern void __init prom_init_env(void); +extern void *loongson_fdt_blob; /* irq operation functions */ extern void mach_irq_dispatch(unsigned int pending); diff --git a/arch/mips/include/asm/mach-malta/irq.h b/arch/mips/include/asm/mach-malta/irq.h index af9eeea250ed..e1bd4298b606 100644 --- a/arch/mips/include/asm/mach-malta/irq.h +++ b/arch/mips/include/asm/mach-malta/irq.h @@ -5,6 +5,6 @@ #define NR_IRQS 256 -#include_next <irq.h> +#include <asm/mach-generic/irq.h> #endif /* __ASM_MACH_MIPS_IRQ_H */ diff --git a/arch/mips/include/asm/mach-pic32/irq.h b/arch/mips/include/asm/mach-pic32/irq.h index d2396941ed2a..ddaf999bc650 100644 --- a/arch/mips/include/asm/mach-pic32/irq.h +++ b/arch/mips/include/asm/mach-pic32/irq.h @@ -9,6 +9,6 @@ #define NR_IRQS 256 #define MIPS_CPU_IRQ_BASE 0 -#include_next <irq.h> +#include <asm/mach-generic/irq.h> #endif /* __ASM_MACH_PIC32_IRQ_H */ diff --git a/arch/mips/include/asm/mach-pistachio/irq.h b/arch/mips/include/asm/mach-pistachio/irq.h index 93bc380f9536..74ac016503ad 100644 --- a/arch/mips/include/asm/mach-pistachio/irq.h +++ b/arch/mips/include/asm/mach-pistachio/irq.h @@ -10,6 +10,6 @@ #define NR_IRQS 256 -#include_next <irq.h> +#include <asm/mach-generic/irq.h> #endif /* __ASM_MACH_PISTACHIO_IRQ_H */ diff --git a/arch/mips/include/asm/mach-ralink/irq.h b/arch/mips/include/asm/mach-ralink/irq.h index 86473e3999aa..2262243d19c9 100644 --- a/arch/mips/include/asm/mach-ralink/irq.h +++ b/arch/mips/include/asm/mach-ralink/irq.h @@ -5,6 +5,6 @@ #define GIC_NUM_INTRS 64 #define NR_IRQS 256 -#include_next <irq.h> +#include <asm/mach-generic/irq.h> #endif diff --git a/arch/mips/include/asm/mach-rm/mc146818rtc.h b/arch/mips/include/asm/mach-rm/mc146818rtc.h index 145bce096fe9..a074f4f84f75 100644 --- a/arch/mips/include/asm/mach-rm/mc146818rtc.h +++ b/arch/mips/include/asm/mach-rm/mc146818rtc.h @@ -16,6 +16,6 @@ #define mc146818_decode_year(year) ((year) + 1980) #endif -#include_next <mc146818rtc.h> +#include <asm/mach-generic/mc146818rtc.h> #endif /* __ASM_MACH_RM_MC146818RTC_H */ diff --git a/arch/mips/include/asm/mach-vr41xx/irq.h b/arch/mips/include/asm/mach-vr41xx/irq.h index 3d63afae37a8..4281b2b9344d 100644 --- a/arch/mips/include/asm/mach-vr41xx/irq.h +++ b/arch/mips/include/asm/mach-vr41xx/irq.h @@ -4,6 +4,6 @@ #include <asm/vr41xx/irq.h> /* for MIPS_CPU_IRQ_BASE */ -#include_next <irq.h> +#include <asm/mach-generic/irq.h> #endif /* __ASM_MACH_VR41XX_IRQ_H */ diff --git a/arch/mips/include/asm/mach-xilfpga/irq.h b/arch/mips/include/asm/mach-xilfpga/irq.h index b8e93fa8adcf..15ad29ec1dee 100644 --- a/arch/mips/include/asm/mach-xilfpga/irq.h +++ b/arch/mips/include/asm/mach-xilfpga/irq.h @@ -9,6 +9,6 @@ #define NR_IRQS 32 -#include_next <irq.h> +#include <asm/mach-generic/irq.h> #endif /* __MIPS_ASM_MACH_XILFPGA_IRQ_H__ */ diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 4c9cc667f3ed..856e12f6063d 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -254,13 +254,13 @@ struct thread_struct { #ifdef CONFIG_MIPS_FP_SUPPORT /* Saved fpu/fpu emulator stuff. */ struct mips_fpu_struct fpu FPU_ALIGN; -#endif /* Assigned branch delay slot 'emulation' frame */ atomic_t bd_emu_frame; /* PC of the branch from a branch delay slot 'emulation' */ unsigned long bd_emu_branch_pc; /* PC to continue from following a branch delay slot 'emulation' */ unsigned long bd_emu_cont_pc; +#endif #ifdef CONFIG_MIPS_MT_FPAFF /* Emulated instruction count */ unsigned long emulated_fp; @@ -303,7 +303,11 @@ struct thread_struct { .fpr = {{{0,},},}, \ .fcr31 = 0, \ .msacsr = 0, \ - }, + }, \ + /* Delay slot emulation */ \ + .bd_emu_frame = ATOMIC_INIT(BD_EMUFRAME_NONE), \ + .bd_emu_branch_pc = 0, \ + .bd_emu_cont_pc = 0, #else # define FPU_INIT #endif @@ -335,10 +339,6 @@ struct thread_struct { * FPU affinity state (null if not FPAFF) \ */ \ FPAFF_INIT \ - /* Delay slot emulation */ \ - .bd_emu_frame = ATOMIC_INIT(BD_EMUFRAME_NONE), \ - .bd_emu_branch_pc = 0, \ - .bd_emu_cont_pc = 0, \ /* \ * Saved DSP stuff \ */ \ diff --git a/arch/mips/include/asm/sni.h b/arch/mips/include/asm/sni.h index a107201a2e1e..7dfa297ce597 100644 --- a/arch/mips/include/asm/sni.h +++ b/arch/mips/include/asm/sni.h @@ -11,6 +11,8 @@ #ifndef __ASM_SNI_H #define __ASM_SNI_H +#include <linux/irqreturn.h> + extern unsigned int sni_brd_type; #define SNI_BRD_10 2 @@ -239,6 +241,6 @@ static inline int sni_eisa_root_init(void) /* common irq stuff */ extern void (*sni_hwint)(void); -extern struct irqaction sni_isa_irq; +extern irqreturn_t sni_isa_irq_handler(int dummy, void *p); #endif /* __ASM_SNI_H */ diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c index 5d6828b2a750..04b9c4068493 100644 --- a/arch/mips/jazz/irq.c +++ b/arch/mips/jazz/irq.c @@ -125,24 +125,18 @@ static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static struct irqaction r4030_timer_irqaction = { - .handler = r4030_timer_interrupt, - .flags = IRQF_TIMER, - .name = "R4030 timer", -}; - void __init plat_time_init(void) { struct clock_event_device *cd = &r4030_clockevent; - struct irqaction *action = &r4030_timer_irqaction; unsigned int cpu = smp_processor_id(); BUG_ON(HZ != 100); cd->cpumask = cpumask_of(cpu); clockevents_register_device(cd); - action->dev_id = cd; - setup_irq(JAZZ_TIMER_IRQ, action); + if (request_irq(JAZZ_TIMER_IRQ, r4030_timer_interrupt, IRQF_TIMER, + "R4030 timer", cd)) + pr_err("Failed to register R4030 timer interrupt\n"); /* * Set clock to 100Hz. diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c index 5476899f0882..605a84a250bf 100644 --- a/arch/mips/jz4740/time.c +++ b/arch/mips/jz4740/time.c @@ -4,8 +4,8 @@ * JZ4740 platform time support */ -#include <linux/clk-provider.h> #include <linux/clocksource.h> +#include <linux/of_clk.h> #include <asm/mach-jz4740/timer.h> diff --git a/arch/mips/kernel/cevt-bcm1480.c b/arch/mips/kernel/cevt-bcm1480.c index b3e8c11a8fa5..d39a2963b451 100644 --- a/arch/mips/kernel/cevt-bcm1480.c +++ b/arch/mips/kernel/cevt-bcm1480.c @@ -91,16 +91,15 @@ static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) } static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent); -static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction); static DEFINE_PER_CPU(char [18], sibyte_hpt_name); void sb1480_clockevent_init(void) { unsigned int cpu = smp_processor_id(); unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu; - struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu); struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu); unsigned char *name = per_cpu(sibyte_hpt_name, cpu); + unsigned long flags = IRQF_PERCPU | IRQF_TIMER; BUG_ON(cpu > 3); /* Only have 4 general purpose timers */ @@ -133,11 +132,7 @@ void sb1480_clockevent_init(void) bcm1480_unmask_irq(cpu, irq); - action->handler = sibyte_counter_handler; - action->flags = IRQF_PERCPU | IRQF_TIMER; - action->name = name; - action->dev_id = cd; - irq_set_affinity(irq, cpumask_of(cpu)); - setup_irq(irq, action); + if (request_irq(irq, sibyte_counter_handler, flags, name, cd)) + pr_err("Failed to request irq %d (%s)\n", irq, name); } diff --git a/arch/mips/kernel/cevt-ds1287.c b/arch/mips/kernel/cevt-ds1287.c index 1e1edab4a63f..9a47fbcd4638 100644 --- a/arch/mips/kernel/cevt-ds1287.c +++ b/arch/mips/kernel/cevt-ds1287.c @@ -100,14 +100,9 @@ static irqreturn_t ds1287_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static struct irqaction ds1287_irqaction = { - .handler = ds1287_interrupt, - .flags = IRQF_PERCPU | IRQF_TIMER, - .name = "ds1287", -}; - int __init ds1287_clockevent_init(int irq) { + unsigned long flags = IRQF_PERCPU | IRQF_TIMER; struct clock_event_device *cd; cd = &ds1287_clockevent; @@ -122,5 +117,5 @@ int __init ds1287_clockevent_init(int irq) clockevents_register_device(&ds1287_clockevent); - return setup_irq(irq, &ds1287_irqaction); + return request_irq(irq, ds1287_interrupt, flags, "ds1287", NULL); } diff --git a/arch/mips/kernel/cevt-gt641xx.c b/arch/mips/kernel/cevt-gt641xx.c index eb53548d2538..5b132e8c51da 100644 --- a/arch/mips/kernel/cevt-gt641xx.c +++ b/arch/mips/kernel/cevt-gt641xx.c @@ -120,12 +120,6 @@ static irqreturn_t gt641xx_timer0_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static struct irqaction gt641xx_timer0_irqaction = { - .handler = gt641xx_timer0_interrupt, - .flags = IRQF_PERCPU | IRQF_TIMER, - .name = "gt641xx_timer0", -}; - static int __init gt641xx_timer0_clockevent_init(void) { struct clock_event_device *cd; @@ -146,6 +140,7 @@ static int __init gt641xx_timer0_clockevent_init(void) clockevents_register_device(>641xx_timer0_clockevent); - return setup_irq(GT641XX_TIMER0_IRQ, >641xx_timer0_irqaction); + return request_irq(GT641XX_TIMER0_IRQ, gt641xx_timer0_interrupt, + IRQF_PERCPU | IRQF_TIMER, "gt641xx_timer0", NULL); } arch_initcall(gt641xx_timer0_clockevent_init); diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index dd6a18bc10ab..17a9cbb8b3df 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -252,6 +252,7 @@ unsigned int __weak get_c0_compare_int(void) int r4k_clockevent_init(void) { + unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED; unsigned int cpu = smp_processor_id(); struct clock_event_device *cd; unsigned int irq, min_delta; @@ -291,7 +292,9 @@ int r4k_clockevent_init(void) cp0_timer_irq_installed = 1; - setup_irq(irq, &c0_compare_irqaction); + if (request_irq(irq, c0_compare_interrupt, flags, "timer", + c0_compare_interrupt)) + pr_err("Failed to request irq %d (timer)\n", irq); return 0; } diff --git a/arch/mips/kernel/cevt-sb1250.c b/arch/mips/kernel/cevt-sb1250.c index e1a08606c27e..0451273fab9f 100644 --- a/arch/mips/kernel/cevt-sb1250.c +++ b/arch/mips/kernel/cevt-sb1250.c @@ -90,16 +90,15 @@ static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) } static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent); -static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction); static DEFINE_PER_CPU(char [18], sibyte_hpt_name); void sb1250_clockevent_init(void) { unsigned int cpu = smp_processor_id(); unsigned int irq = K_INT_TIMER_0 + cpu; - struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu); struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu); unsigned char *name = per_cpu(sibyte_hpt_name, cpu); + unsigned long flags = IRQF_PERCPU | IRQF_TIMER; /* Only have 4 general purpose timers, and we use last one as hpt */ BUG_ON(cpu > 2); @@ -133,11 +132,7 @@ void sb1250_clockevent_init(void) sb1250_unmask_irq(cpu, irq); - action->handler = sibyte_counter_handler; - action->flags = IRQF_PERCPU | IRQF_TIMER; - action->name = name; - action->dev_id = cd; - irq_set_affinity(irq, cpumask_of(cpu)); - setup_irq(irq, action); + if (request_irq(irq, sibyte_counter_handler, flags, name, cd)) + pr_err("Failed to request irq %d (%s)\n", irq, name); } diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c index 7b17c8f5009d..5709469c21ff 100644 --- a/arch/mips/kernel/cevt-txx9.c +++ b/arch/mips/kernel/cevt-txx9.c @@ -174,13 +174,6 @@ static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static struct irqaction txx9tmr_irq = { - .handler = txx9tmr_interrupt, - .flags = IRQF_PERCPU | IRQF_TIMER, - .name = "txx9tmr", - .dev_id = &txx9_clock_event_device, -}; - void __init txx9_clockevent_init(unsigned long baseaddr, int irq, unsigned int imbusclk) { @@ -202,7 +195,9 @@ void __init txx9_clockevent_init(unsigned long baseaddr, int irq, cd->irq = irq; cd->cpumask = cpumask_of(0), clockevents_register_device(cd); - setup_irq(irq, &txx9tmr_irq); + if (request_irq(irq, txx9tmr_interrupt, IRQF_PERCPU | IRQF_TIMER, + "txx9tmr", &txx9_clock_event_device)) + pr_err("Failed to request irq %d (txx9tmr)\n", irq); printk(KERN_INFO "TXx9: clockevent device at 0x%lx, irq %d\n", baseaddr, irq); } diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 6ab6b03d35ba..f21a2304401f 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -513,6 +513,13 @@ static inline void set_elf_platform(int cpu, const char *plat) __elf_platform = plat; } +static inline void set_elf_base_platform(const char *plat) +{ + if (__elf_base_platform == NULL) { + __elf_base_platform = plat; + } +} + static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) { #ifdef __NEED_VMBITS_PROBE @@ -527,36 +534,46 @@ static void set_isa(struct cpuinfo_mips *c, unsigned int isa) switch (isa) { case MIPS_CPU_ISA_M64R2: c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; + set_elf_base_platform("mips64r2"); /* fall through */ case MIPS_CPU_ISA_M64R1: c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; + set_elf_base_platform("mips64"); /* fall through */ case MIPS_CPU_ISA_V: c->isa_level |= MIPS_CPU_ISA_V; + set_elf_base_platform("mips5"); /* fall through */ case MIPS_CPU_ISA_IV: c->isa_level |= MIPS_CPU_ISA_IV; + set_elf_base_platform("mips4"); /* fall through */ case MIPS_CPU_ISA_III: c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; + set_elf_base_platform("mips3"); break; /* R6 incompatible with everything else */ case MIPS_CPU_ISA_M64R6: c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; + set_elf_base_platform("mips64r6"); /* fall through */ case MIPS_CPU_ISA_M32R6: c->isa_level |= MIPS_CPU_ISA_M32R6; + set_elf_base_platform("mips32r6"); /* Break here so we don't add incompatible ISAs */ break; case MIPS_CPU_ISA_M32R2: c->isa_level |= MIPS_CPU_ISA_M32R2; + set_elf_base_platform("mips32r2"); /* fall through */ case MIPS_CPU_ISA_M32R1: c->isa_level |= MIPS_CPU_ISA_M32R1; + set_elf_base_platform("mips32"); /* fall through */ case MIPS_CPU_ISA_II: c->isa_level |= MIPS_CPU_ISA_II; + set_elf_base_platform("mips2"); break; } } @@ -2113,6 +2130,7 @@ EXPORT_SYMBOL(__ua_limit); const char *__cpu_name[NR_CPUS]; const char *__elf_platform; +const char *__elf_base_platform; void cpu_probe(void) { diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c index df7ddd246eaa..ca21210e06b5 100644 --- a/arch/mips/kernel/i8253.c +++ b/arch/mips/kernel/i8253.c @@ -18,16 +18,13 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static struct irqaction irq0 = { - .handler = timer_interrupt, - .flags = IRQF_NOBALANCING | IRQF_TIMER, - .name = "timer" -}; - void __init setup_pit_timer(void) { + unsigned long flags = IRQF_NOBALANCING | IRQF_TIMER; + clockevent_i8253_init(true); - setup_irq(0, &irq0); + if (request_irq(0, timer_interrupt, flags, "timer", NULL)) + pr_err("Failed to request irq 0 (timer)\n"); } static int __init init_pit_clocksource(void) diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 339870ed92f7..b2a797557825 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -75,7 +75,9 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) lose_fpu(0); clear_thread_flag(TIF_MSA_CTX_LIVE); clear_used_math(); +#ifdef CONFIG_MIPS_FP_SUPPORT atomic_set(¤t->thread.bd_emu_frame, BD_EMUFRAME_NONE); +#endif init_dsp(); regs->cp0_epc = pc; regs->regs[29] = sp; @@ -176,7 +178,9 @@ int copy_thread_tls(unsigned long clone_flags, unsigned long usp, clear_tsk_thread_flag(p, TIF_FPUBOUND); #endif /* CONFIG_MIPS_MT_FPAFF */ +#ifdef CONFIG_MIPS_FP_SUPPORT atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE); +#endif if (clone_flags & CLONE_SETTLS) ti->tp_value = tls; @@ -650,8 +654,10 @@ unsigned long mips_stack_top(void) { unsigned long top = TASK_SIZE & PAGE_MASK; - /* One page for branch delay slot "emulation" */ - top -= PAGE_SIZE; + if (IS_ENABLED(CONFIG_MIPS_FP_SUPPORT)) { + /* One page for branch delay slot "emulation" */ + top -= PAGE_SIZE; + } /* Space for the VDSO, data page & GIC user page */ top -= PAGE_ALIGN(current->thread.abi->vdso->size); diff --git a/arch/mips/kernel/rtlx-mt.c b/arch/mips/kernel/rtlx-mt.c index cb95470e2e69..38c6925a1bea 100644 --- a/arch/mips/kernel/rtlx-mt.c +++ b/arch/mips/kernel/rtlx-mt.c @@ -51,11 +51,6 @@ static irqreturn_t rtlx_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static struct irqaction rtlx_irq = { - .handler = rtlx_interrupt, - .name = "RTLX", -}; - static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ; void _interrupt_sp(void) @@ -124,8 +119,7 @@ int __init rtlx_module_init(void) goto out_class; } - rtlx_irq.dev_id = rtlx; - err = setup_irq(rtlx_irq_num, &rtlx_irq); + err = request_irq(rtlx_irq_num, rtlx_interrupt, 0, "RTLX", rtlx); if (err) goto out_class; diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index a7b469d89e2c..10bef8f78e7c 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -28,6 +28,7 @@ #include <linux/decompress/generic.h> #include <linux/of_fdt.h> #include <linux/of_reserved_mem.h> +#include <linux/dmi.h> #include <asm/addrspace.h> #include <asm/bootinfo.h> @@ -799,6 +800,7 @@ void __init setup_arch(char **cmdline_p) #endif arch_mem_init(cmdline_p); + dmi_setup(); resource_init(); plat_smp_setup(); diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 0def6242b3ea..48d84d5fcc36 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -207,25 +207,13 @@ static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static struct irqaction irq_resched = { - .handler = ipi_resched_interrupt, - .flags = IRQF_PERCPU, - .name = "IPI resched" -}; - -static struct irqaction irq_call = { - .handler = ipi_call_interrupt, - .flags = IRQF_PERCPU, - .name = "IPI call" -}; - -static void smp_ipi_init_one(unsigned int virq, - struct irqaction *action) +static void smp_ipi_init_one(unsigned int virq, const char *name, + irq_handler_t handler) { int ret; irq_set_handler(virq, handle_percpu_irq); - ret = setup_irq(virq, action); + ret = request_irq(virq, handler, IRQF_PERCPU, name, NULL); BUG_ON(ret); } @@ -278,12 +266,15 @@ int mips_smp_ipi_allocate(const struct cpumask *mask) int cpu; for_each_cpu(cpu, mask) { - smp_ipi_init_one(call_virq + cpu, &irq_call); - smp_ipi_init_one(sched_virq + cpu, &irq_resched); + smp_ipi_init_one(call_virq + cpu, "IPI call", + ipi_call_interrupt); + smp_ipi_init_one(sched_virq + cpu, "IPI resched", + ipi_resched_interrupt); } } else { - smp_ipi_init_one(call_virq, &irq_call); - smp_ipi_init_one(sched_virq, &irq_resched); + smp_ipi_init_one(call_virq, "IPI call", ipi_call_interrupt); + smp_ipi_init_one(sched_virq, "IPI resched", + ipi_resched_interrupt); } return 0; @@ -311,8 +302,8 @@ int mips_smp_ipi_free(const struct cpumask *mask) int cpu; for_each_cpu(cpu, mask) { - remove_irq(call_virq + cpu, &irq_call); - remove_irq(sched_virq + cpu, &irq_resched); + free_irq(call_virq + cpu, NULL); + free_irq(sched_virq + cpu, NULL); } } irq_destroy_ipi(call_virq, mask); diff --git a/arch/mips/kernel/vdso.c b/arch/mips/kernel/vdso.c index bc35f8499111..3adb7354bc01 100644 --- a/arch/mips/kernel/vdso.c +++ b/arch/mips/kernel/vdso.c @@ -71,10 +71,12 @@ subsys_initcall(init_vdso); static unsigned long vdso_base(void) { - unsigned long base; + unsigned long base = STACK_TOP; - /* Skip the delay slot emulation page */ - base = STACK_TOP + PAGE_SIZE; + if (IS_ENABLED(CONFIG_MIPS_FP_SUPPORT)) { + /* Skip the delay slot emulation page */ + base += PAGE_SIZE; + } if (current->flags & PF_RANDOMIZE) { base += get_random_int() & (VDSO_RANDOMIZE_SIZE - 1); @@ -95,14 +97,16 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) if (down_write_killable(&mm->mmap_sem)) return -EINTR; - /* Map delay slot emulation page */ - base = mmap_region(NULL, STACK_TOP, PAGE_SIZE, - VM_READ | VM_EXEC | - VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC, - 0, NULL); - if (IS_ERR_VALUE(base)) { - ret = base; - goto out; + if (IS_ENABLED(CONFIG_MIPS_FP_SUPPORT)) { + /* Map delay slot emulation page */ + base = mmap_region(NULL, STACK_TOP, PAGE_SIZE, + VM_READ | VM_EXEC | + VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC, + 0, NULL); + if (IS_ERR_VALUE(base)) { + ret = base; + goto out; + } } /* diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c index 0f3a8975081d..7965bbd0d319 100644 --- a/arch/mips/lasat/interrupt.c +++ b/arch/mips/lasat/interrupt.c @@ -90,14 +90,9 @@ asmlinkage void plat_irq_dispatch(void) } } -static struct irqaction cascade = { - .handler = no_action, - .name = "cascade", - .flags = IRQF_NO_THREAD, -}; - void __init arch_init_irq(void) { + int irq = LASAT_CASCADE_IRQ; int i; if (IS_LASAT_200()) { @@ -119,5 +114,6 @@ void __init arch_init_irq(void) for (i = LASAT_IRQ_BASE; i <= LASAT_IRQ_END; i++) irq_set_chip_and_handler(i, &lasat_irq_type, handle_level_irq); - setup_irq(LASAT_CASCADE_IRQ, &cascade); + if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL)) + pr_err("Failed to request irq %d (cascade)\n", irq); } diff --git a/arch/mips/lib/delay.c b/arch/mips/lib/delay.c index 68c495ed71e3..2e8dfc1d59c8 100644 --- a/arch/mips/lib/delay.c +++ b/arch/mips/lib/delay.c @@ -24,6 +24,8 @@ #define GCC_DADDI_IMM_ASM() "r" #endif +#ifndef CONFIG_HAVE_PLAT_DELAY + void __delay(unsigned long loops) { __asm__ __volatile__ ( @@ -63,3 +65,5 @@ void __ndelay(unsigned long ns) __delay((ns * 0x00000005ull * HZ * lpj) >> 32); } EXPORT_SYMBOL(__ndelay); + +#endif diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S index f7994d936505..88065ee433cd 100644 --- a/arch/mips/lib/memcpy.S +++ b/arch/mips/lib/memcpy.S @@ -598,6 +598,7 @@ SEXC(1) nop .endm +#ifndef CONFIG_HAVE_PLAT_MEMCPY .align 5 LEAF(memmove) EXPORT_SYMBOL(memmove) @@ -665,6 +666,8 @@ EXPORT_SYMBOL(__copy_user) /* Legacy Mode, user <-> user */ __BUILD_COPY_USER LEGACY_MODE USEROP USEROP +#endif + #ifdef CONFIG_EVA /* diff --git a/arch/mips/loongson2ef/common/bonito-irq.c b/arch/mips/loongson2ef/common/bonito-irq.c index 82352cc25e4c..c06ad412ee20 100644 --- a/arch/mips/loongson2ef/common/bonito-irq.c +++ b/arch/mips/loongson2ef/common/bonito-irq.c @@ -30,11 +30,6 @@ static struct irq_chip bonito_irq_type = { .irq_unmask = bonito_irq_enable, }; -static struct irqaction __maybe_unused dma_timeout_irqaction = { - .handler = no_action, - .name = "dma_timeout", -}; - void bonito_irq_init(void) { u32 i; @@ -44,6 +39,8 @@ void bonito_irq_init(void) handle_level_irq); #ifdef CONFIG_CPU_LOONGSON2E - setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction); + i = LOONGSON_IRQ_BASE + 10; + if (request_irq(i, no_action, 0, "dma_timeout", NULL)) + pr_err("Failed to request irq %d (dma_timeout)\n", i); #endif } diff --git a/arch/mips/loongson2ef/common/cs5536/cs5536_mfgpt.c b/arch/mips/loongson2ef/common/cs5536/cs5536_mfgpt.c index 30af1b7c7529..f21a540a1dd2 100644 --- a/arch/mips/loongson2ef/common/cs5536/cs5536_mfgpt.c +++ b/arch/mips/loongson2ef/common/cs5536/cs5536_mfgpt.c @@ -100,12 +100,6 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static struct irqaction irq5 = { - .handler = timer_interrupt, - .flags = IRQF_NOBALANCING | IRQF_TIMER, - .name = "timer" -}; - /* * Initialize the conversion factor and the min/max deltas of the clock event * structure and register the clock event source with the framework. @@ -134,7 +128,9 @@ void __init setup_mfgpt0_timer(void) clockevents_register_device(cd); - setup_irq(CS5536_MFGPT_INTR, &irq5); + if (request_irq(CS5536_MFGPT_INTR, timer_interrupt, + IRQF_NOBALANCING | IRQF_TIMER, "timer", NULL)) + pr_err("Failed to register timer interrupt\n"); } /* diff --git a/arch/mips/loongson2ef/fuloong-2e/irq.c b/arch/mips/loongson2ef/fuloong-2e/irq.c index 32278e7bf85c..305aa2eb74ad 100644 --- a/arch/mips/loongson2ef/fuloong-2e/irq.c +++ b/arch/mips/loongson2ef/fuloong-2e/irq.c @@ -35,14 +35,10 @@ asmlinkage void mach_irq_dispatch(unsigned int pending) spurious_interrupt(); } -static struct irqaction cascade_irqaction = { - .handler = no_action, - .name = "cascade", - .flags = IRQF_NO_THREAD, -}; - void __init mach_init_irq(void) { + int irq; + /* init all controller * 0-15 ------> i8259 interrupt * 16-23 ------> mips cpu interrupt @@ -59,7 +55,11 @@ void __init mach_init_irq(void) bonito_irq_init(); /* bonito irq at IP2 */ - setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction); + irq = MIPS_CPU_IRQ_BASE + 2; + if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL)) + pr_err("Failed to request irq %d (cascade)\n", irq); /* 8259 irq at IP5 */ - setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction); + irq = MIPS_CPU_IRQ_BASE + 5; + if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL)) + pr_err("Failed to request irq %d (cascade)\n", irq); } diff --git a/arch/mips/loongson2ef/lemote-2f/irq.c b/arch/mips/loongson2ef/lemote-2f/irq.c index c58a044c6c07..6f00579971a3 100644 --- a/arch/mips/loongson2ef/lemote-2f/irq.c +++ b/arch/mips/loongson2ef/lemote-2f/irq.c @@ -90,18 +90,6 @@ static irqreturn_t ip6_action(int cpl, void *dev_id) return IRQ_HANDLED; } -static struct irqaction ip6_irqaction = { - .handler = ip6_action, - .name = "cascade", - .flags = IRQF_SHARED | IRQF_NO_THREAD, -}; - -static struct irqaction cascade_irqaction = { - .handler = no_action, - .name = "cascade", - .flags = IRQF_NO_THREAD | IRQF_NO_SUSPEND, -}; - void __init mach_init_irq(void) { /* init all controller @@ -120,7 +108,11 @@ void __init mach_init_irq(void) bonito_irq_init(); /* setup north bridge irq (bonito) */ - setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &ip6_irqaction); + if (request_irq(LOONGSON_NORTH_BRIDGE_IRQ, ip6_action, + IRQF_SHARED | IRQF_NO_THREAD, "cascade", ip6_action)) + pr_err("Failed to register north bridge cascade interrupt\n"); /* setup source bridge irq (i8259) */ - setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction); + if (request_irq(LOONGSON_SOUTH_BRIDGE_IRQ, no_action, + IRQF_NO_THREAD | IRQF_NO_SUSPEND, "cascade", NULL)) + pr_err("Failed to register south bridge cascade interrupt\n"); } diff --git a/arch/mips/loongson32/common/irq.c b/arch/mips/loongson32/common/irq.c index 168d221d4178..9a50070f74f7 100644 --- a/arch/mips/loongson32/common/irq.c +++ b/arch/mips/loongson32/common/irq.c @@ -149,12 +149,6 @@ asmlinkage void plat_irq_dispatch(void) } -static struct irqaction cascade_irqaction = { - .handler = no_action, - .name = "cascade", - .flags = IRQF_NO_THREAD, -}; - static void __init ls1x_irq_init(int base) { int n; @@ -176,12 +170,17 @@ static void __init ls1x_irq_init(int base) handle_level_irq); } - setup_irq(INT0_IRQ, &cascade_irqaction); - setup_irq(INT1_IRQ, &cascade_irqaction); - setup_irq(INT2_IRQ, &cascade_irqaction); - setup_irq(INT3_IRQ, &cascade_irqaction); + if (request_irq(INT0_IRQ, no_action, IRQF_NO_THREAD, "cascade", NULL)) + pr_err("Failed to request irq %d (cascade)\n", INT0_IRQ); + if (request_irq(INT1_IRQ, no_action, IRQF_NO_THREAD, "cascade", NULL)) + pr_err("Failed to request irq %d (cascade)\n", INT1_IRQ); + if (request_irq(INT2_IRQ, no_action, IRQF_NO_THREAD, "cascade", NULL)) + pr_err("Failed to request irq %d (cascade)\n", INT2_IRQ); + if (request_irq(INT3_IRQ, no_action, IRQF_NO_THREAD, "cascade", NULL)) + pr_err("Failed to request irq %d (cascade)\n", INT3_IRQ); #if defined(CONFIG_LOONGSON1_LS1C) - setup_irq(INT4_IRQ, &cascade_irqaction); + if (request_irq(INT4_IRQ, no_action, IRQF_NO_THREAD, "cascade", NULL)) + pr_err("Failed to request irq %d (cascade)\n", INT4_IRQ); #endif } diff --git a/arch/mips/loongson32/common/time.c b/arch/mips/loongson32/common/time.c index 4cc73f7ac0d4..459b15c96d3b 100644 --- a/arch/mips/loongson32/common/time.c +++ b/arch/mips/loongson32/common/time.c @@ -176,13 +176,6 @@ static struct clock_event_device ls1x_clockevent = { .tick_resume = ls1x_clockevent_tick_resume, }; -static struct irqaction ls1x_pwmtimer_irqaction = { - .name = "ls1x-pwmtimer", - .handler = ls1x_clockevent_isr, - .dev_id = &ls1x_clockevent, - .flags = IRQF_PERCPU | IRQF_TIMER, -}; - static void __init ls1x_time_init(void) { struct clock_event_device *cd = &ls1x_clockevent; @@ -206,7 +199,10 @@ static void __init ls1x_time_init(void) if (ret) panic(KERN_ERR "Failed to register clocksource: %d\n", ret); - setup_irq(LS1X_TIMER_IRQ, &ls1x_pwmtimer_irqaction); + if (request_irq(LS1X_TIMER_IRQ, ls1x_clockevent_isr, + IRQF_PERCPU | IRQF_TIMER, "ls1x-pwmtimer", + &ls1x_clockevent)) + pr_err("Failed to register ls1x-pwmtimer interrupt\n"); } #endif /* CONFIG_CEVT_CSRC_LS1X */ diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile index 7821891bc5d0..b7f40b179c71 100644 --- a/arch/mips/loongson64/Makefile +++ b/arch/mips/loongson64/Makefile @@ -2,7 +2,7 @@ # # Makefile for Loongson-3 family machines # -obj-$(CONFIG_MACH_LOONGSON64) += irq.o cop2-ex.o platform.o acpi_init.o dma.o \ +obj-$(CONFIG_MACH_LOONGSON64) += cop2-ex.o platform.o acpi_init.o dma.o \ setup.o init.o env.o time.o reset.o \ obj-$(CONFIG_SMP) += smp.o diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c index 0daeb7bcf023..2554ef11170d 100644 --- a/arch/mips/loongson64/env.c +++ b/arch/mips/loongson64/env.c @@ -17,6 +17,7 @@ #include <asm/bootinfo.h> #include <loongson.h> #include <boot_param.h> +#include <builtin_dtbs.h> #include <workarounds.h> u32 cpu_clock_freq; @@ -120,6 +121,28 @@ void __init prom_init_env(void) loongson_sysconf.cores_per_node - 1) / loongson_sysconf.cores_per_node; + if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) { + switch (read_c0_prid() & PRID_REV_MASK) { + case PRID_REV_LOONGSON3A_R1: + case PRID_REV_LOONGSON3A_R2_0: + case PRID_REV_LOONGSON3A_R2_1: + case PRID_REV_LOONGSON3A_R3_0: + case PRID_REV_LOONGSON3A_R3_1: + loongson_fdt_blob = __dtb_loongson3_4core_rs780e_begin; + break; + case PRID_REV_LOONGSON3B_R1: + case PRID_REV_LOONGSON3B_R2: + loongson_fdt_blob = __dtb_loongson3_8core_rs780e_begin; + break; + default: + break; + } + } + + + if (!loongson_fdt_blob) + pr_err("Failed to determine built-in Loongson64 dtb\n"); + loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr; loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr; loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr; diff --git a/arch/mips/loongson64/hpet.c b/arch/mips/loongson64/hpet.c index ed15430ad64f..e4282592575b 100644 --- a/arch/mips/loongson64/hpet.c +++ b/arch/mips/loongson64/hpet.c @@ -187,12 +187,6 @@ static irqreturn_t hpet_irq_handler(int irq, void *data) return IRQ_NONE; } -static struct irqaction hpet_irq = { - .handler = hpet_irq_handler, - .flags = IRQF_NOBALANCING | IRQF_TIMER, - .name = "hpet", -}; - /* * hpet address assignation and irq setting should be done in bios. * but pmon don't do this, we just setup here directly. @@ -224,6 +218,7 @@ static void hpet_setup(void) void __init setup_hpet_timer(void) { + unsigned long flags = IRQF_NOBALANCING | IRQF_TIMER; unsigned int cpu = smp_processor_id(); struct clock_event_device *cd; @@ -247,7 +242,8 @@ void __init setup_hpet_timer(void) cd->min_delta_ticks = HPET_MIN_PROG_DELTA; clockevents_register_device(cd); - setup_irq(HPET_T0_IRQ, &hpet_irq); + if (request_irq(HPET_T0_IRQ, hpet_irq_handler, flags, "hpet", NULL)) + pr_err("Failed to request irq %d (hpet)\n", HPET_T0_IRQ); pr_info("hpet clock event device register\n"); } diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c index 5ac1a0f35ca4..da38944471f4 100644 --- a/arch/mips/loongson64/init.c +++ b/arch/mips/loongson64/init.c @@ -4,6 +4,7 @@ * Author: Wu Zhangjin, wuzhangjin@gmail.com */ +#include <linux/irqchip.h> #include <linux/memblock.h> #include <asm/bootinfo.h> #include <asm/traps.h> @@ -44,3 +45,8 @@ void __init prom_init(void) void __init prom_free_prom_memory(void) { } + +void __init arch_init_irq(void) +{ + irqchip_init(); +} diff --git a/arch/mips/loongson64/irq.c b/arch/mips/loongson64/irq.c deleted file mode 100644 index 79ad797497e4..000000000000 --- a/arch/mips/loongson64/irq.c +++ /dev/null @@ -1,162 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include <loongson.h> -#include <irq.h> -#include <linux/interrupt.h> -#include <linux/init.h> - -#include <asm/irq_cpu.h> -#include <asm/i8259.h> -#include <asm/mipsregs.h> - -#include "smp.h" - -extern void loongson3_send_irq_by_ipi(int cpu, int irqs); - -unsigned int irq_cpu[16] = {[0 ... 15] = -1}; -unsigned int ht_irq[] = {0, 1, 3, 4, 5, 6, 7, 8, 12, 14, 15}; -unsigned int local_irq = 1<<0 | 1<<1 | 1<<2 | 1<<7 | 1<<8 | 1<<12; - -int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, - bool force) -{ - unsigned int cpu; - struct cpumask new_affinity; - - /* I/O devices are connected on package-0 */ - cpumask_copy(&new_affinity, affinity); - for_each_cpu(cpu, affinity) - if (cpu_data[cpu].package > 0) - cpumask_clear_cpu(cpu, &new_affinity); - - if (cpumask_empty(&new_affinity)) - return -EINVAL; - - cpumask_copy(d->common->affinity, &new_affinity); - - return IRQ_SET_MASK_OK_NOCOPY; -} - -static void ht_irqdispatch(void) -{ - unsigned int i, irq; - struct irq_data *irqd; - struct cpumask affinity; - - irq = LOONGSON_HT1_INT_VECTOR(0); - LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */ - - for (i = 0; i < ARRAY_SIZE(ht_irq); i++) { - if (!(irq & (0x1 << ht_irq[i]))) - continue; - - /* handled by local core */ - if (local_irq & (0x1 << ht_irq[i])) { - do_IRQ(ht_irq[i]); - continue; - } - - irqd = irq_get_irq_data(ht_irq[i]); - cpumask_and(&affinity, irqd->common->affinity, cpu_active_mask); - if (cpumask_empty(&affinity)) { - do_IRQ(ht_irq[i]); - continue; - } - - irq_cpu[ht_irq[i]] = cpumask_next(irq_cpu[ht_irq[i]], &affinity); - if (irq_cpu[ht_irq[i]] >= nr_cpu_ids) - irq_cpu[ht_irq[i]] = cpumask_first(&affinity); - - if (irq_cpu[ht_irq[i]] == 0) { - do_IRQ(ht_irq[i]); - continue; - } - - /* balanced by other cores */ - loongson3_send_irq_by_ipi(irq_cpu[ht_irq[i]], (0x1 << ht_irq[i])); - } -} - -#define UNUSED_IPS (CAUSEF_IP5 | CAUSEF_IP4 | CAUSEF_IP1 | CAUSEF_IP0) - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending; - - pending = read_c0_cause() & read_c0_status() & ST0_IM; - - if (pending & CAUSEF_IP7) - do_IRQ(LOONGSON_TIMER_IRQ); -#if defined(CONFIG_SMP) - if (pending & CAUSEF_IP6) - loongson3_ipi_interrupt(NULL); -#endif - if (pending & CAUSEF_IP3) - ht_irqdispatch(); - if (pending & CAUSEF_IP2) - do_IRQ(LOONGSON_UART_IRQ); - if (pending & UNUSED_IPS) { - pr_err("%s : spurious interrupt\n", __func__); - spurious_interrupt(); - } -} - -static inline void mask_loongson_irq(struct irq_data *d) { } -static inline void unmask_loongson_irq(struct irq_data *d) { } - - /* For MIPS IRQs which shared by all cores */ -static struct irq_chip loongson_irq_chip = { - .name = "Loongson", - .irq_ack = mask_loongson_irq, - .irq_mask = mask_loongson_irq, - .irq_mask_ack = mask_loongson_irq, - .irq_unmask = unmask_loongson_irq, - .irq_eoi = unmask_loongson_irq, -}; - -void irq_router_init(void) -{ - int i; - - /* route LPC int to cpu core0 int 0 */ - LOONGSON_INT_ROUTER_LPC = - LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 0); - /* route HT1 int0 ~ int7 to cpu core0 INT1*/ - for (i = 0; i < 8; i++) - LOONGSON_INT_ROUTER_HT1(i) = - LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 1); - /* enable HT1 interrupt */ - LOONGSON_HT1_INTN_EN(0) = 0xffffffff; - /* enable router interrupt intenset */ - LOONGSON_INT_ROUTER_INTENSET = - LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10; -} - -void __init arch_init_irq(void) -{ - struct irq_chip *chip; - - clear_c0_status(ST0_IM | ST0_BEV); - - irq_router_init(); - mips_cpu_irq_init(); - init_i8259_irqs(); - chip = irq_get_chip(I8259A_IRQ_BASE); - chip->irq_set_affinity = plat_set_irq_affinity; - - irq_set_chip_and_handler(LOONGSON_UART_IRQ, - &loongson_irq_chip, handle_percpu_irq); - irq_set_chip_and_handler(LOONGSON_BRIDGE_IRQ, - &loongson_irq_chip, handle_percpu_irq); - - set_c0_status(STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP6); -} - -#ifdef CONFIG_HOTPLUG_CPU - -void fixup_irqs(void) -{ - irq_cpu_offline(); - clear_c0_status(ST0_IM); -} - -#endif diff --git a/arch/mips/loongson64/numa.c b/arch/mips/loongson64/numa.c index e5b40c5e3296..1ae072df4831 100644 --- a/arch/mips/loongson64/numa.c +++ b/arch/mips/loongson64/numa.c @@ -122,7 +122,7 @@ static unsigned long nid_to_addroffset(unsigned int nid) static void __init szmem(unsigned int node) { u32 i, mem_type; - static unsigned long num_physpages = 0; + static unsigned long num_physpages; u64 node_id, node_psize, start_pfn, end_pfn, mem_start, mem_size; /* Parse memory information and activate */ diff --git a/arch/mips/loongson64/setup.c b/arch/mips/loongson64/setup.c index 4fd27f4f90ed..6fe3ffffcaa6 100644 --- a/arch/mips/loongson64/setup.c +++ b/arch/mips/loongson64/setup.c @@ -8,9 +8,15 @@ #include <asm/wbflush.h> #include <asm/bootinfo.h> +#include <linux/libfdt.h> +#include <linux/of_fdt.h> + +#include <asm/prom.h> #include <loongson.h> +void *loongson_fdt_blob; + static void wbflush_loongson(void) { asm(".set\tpush\n\t" @@ -27,4 +33,14 @@ EXPORT_SYMBOL(__wbflush); void __init plat_mem_setup(void) { + if (loongson_fdt_blob) + __dt_setup_arch(loongson_fdt_blob); +} + +void __init device_tree_init(void) +{ + if (!initial_boot_params) + return; + + unflatten_and_copy_device_tree(); } diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index de8e0741ce2d..e1fe8bbb377d 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -4,6 +4,7 @@ * Author: Chen Huacai, chenhc@lemote.com */ +#include <irq.h> #include <linux/init.h> #include <linux/cpu.h> #include <linux/sched.h> @@ -25,6 +26,8 @@ DEFINE_PER_CPU(int, cpu_state); +#define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6) + static void *ipi_set0_regs[16]; static void *ipi_clear0_regs[16]; static void *ipi_status0_regs[16]; @@ -302,20 +305,13 @@ loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action) ipi_write_action(cpu_logical_map(i), (u32)action); } -#define IPI_IRQ_OFFSET 6 - -void loongson3_send_irq_by_ipi(int cpu, int irqs) -{ - ipi_write_action(cpu_logical_map(cpu), irqs << IPI_IRQ_OFFSET); -} -void loongson3_ipi_interrupt(struct pt_regs *regs) +static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id) { int i, cpu = smp_processor_id(); - unsigned int action, c0count, irqs; + unsigned int action, c0count; action = ipi_read_clear(cpu); - irqs = action >> IPI_IRQ_OFFSET; if (action & SMP_RESCHEDULE_YOURSELF) scheduler_ipi(); @@ -335,13 +331,7 @@ void loongson3_ipi_interrupt(struct pt_regs *regs) __wbflush(); /* Let others see the result ASAP */ } - if (irqs) { - int irq; - while ((irq = ffs(irqs))) { - do_IRQ(irq-1); - irqs &= ~(1<<(irq-1)); - } - } + return IRQ_HANDLED; } #define MAX_LOOPS 800 @@ -438,6 +428,9 @@ static void __init loongson3_smp_setup(void) static void __init loongson3_prepare_cpus(unsigned int max_cpus) { + if (request_irq(LS_IPI_IRQ, loongson3_ipi_interrupt, + IRQF_PERCPU | IRQF_NO_SUSPEND, "SMP_IPI", NULL)) + pr_err("Failed to request IPI IRQ\n"); init_cpu_present(cpu_possible_mask); per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; } @@ -484,7 +477,8 @@ static int loongson3_cpu_disable(void) set_cpu_online(cpu, false); calculate_cpu_foreign_map(); local_irq_save(flags); - fixup_irqs(); + irq_cpu_offline(); + clear_c0_status(ST0_IM); local_irq_restore(flags); local_flush_tlb_all(); diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index 8064821e9805..4baf965e6fe8 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -237,17 +237,17 @@ static void probe_octeon(void) c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways); if (smp_processor_id() == 0) { - pr_notice("Primary instruction cache %ldkB, %s, %d way, " - "%d sets, linesize %d bytes.\n", - icache_size >> 10, - cpu_has_vtag_icache ? + pr_info("Primary instruction cache %ldkB, %s, %d way, " + "%d sets, linesize %d bytes.\n", + icache_size >> 10, + cpu_has_vtag_icache ? "virtually tagged" : "physically tagged", - c->icache.ways, c->icache.sets, c->icache.linesz); + c->icache.ways, c->icache.sets, c->icache.linesz); - pr_notice("Primary data cache %ldkB, %d-way, %d sets, " - "linesize %d bytes.\n", - dcache_size >> 10, c->dcache.ways, - c->dcache.sets, c->dcache.linesz); + pr_info("Primary data cache %ldkB, %d-way, %d sets, " + "linesize %d bytes.\n", + dcache_size >> 10, c->dcache.ways, + c->dcache.sets, c->dcache.linesz); } } diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c index 15bb8cf59828..780dd2a567c1 100644 --- a/arch/mips/mm/c-r3k.c +++ b/arch/mips/mm/c-r3k.c @@ -316,9 +316,9 @@ void r3k_cache_init(void) _dma_cache_wback = r3k_dma_cache_wback_inv; _dma_cache_inv = r3k_dma_cache_wback_inv; - printk("Primary instruction cache %ldkB, linesize %ld bytes.\n", + pr_info("Primary instruction cache %ldkB, linesize %ld bytes.\n", icache_size >> 10, icache_lsize); - printk("Primary data cache %ldkB, linesize %ld bytes.\n", + pr_info("Primary data cache %ldkB, linesize %ld bytes.\n", dcache_size >> 10, dcache_lsize); build_clear_page(); diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 5f3d0103b95d..36a311348739 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -901,6 +901,31 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) __sync(); } +static void prefetch_cache_inv(unsigned long addr, unsigned long size) +{ + unsigned int linesz = cpu_scache_line_size(); + unsigned long addr0 = addr, addr1; + + addr0 &= ~(linesz - 1); + addr1 = (addr0 + size - 1) & ~(linesz - 1); + + protected_writeback_scache_line(addr0); + if (likely(addr1 != addr0)) + protected_writeback_scache_line(addr1); + else + return; + + addr0 += linesz; + if (likely(addr1 != addr0)) + protected_writeback_scache_line(addr0); + else + return; + + addr1 -= linesz; + if (likely(addr1 > addr0)) + protected_writeback_scache_line(addr0); +} + static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) { /* Catch bad driver code */ @@ -908,6 +933,10 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) return; preempt_disable(); + + if (current_cpu_type() == CPU_BMIPS5000) + prefetch_cache_inv(addr, size); + if (cpu_has_inclusive_pcaches) { if (size >= scache_size) { if (current_cpu_type() != CPU_LOONGSON64) @@ -1467,17 +1496,17 @@ static void probe_pcache(void) c->icache.ways = 1; } - printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", - icache_size >> 10, - c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", - way_string[c->icache.ways], c->icache.linesz); + pr_info("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", + icache_size >> 10, + c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", + way_string[c->icache.ways], c->icache.linesz); - printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", - dcache_size >> 10, way_string[c->dcache.ways], - (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", - (c->dcache.flags & MIPS_CACHE_ALIASES) ? + pr_info("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", + dcache_size >> 10, way_string[c->dcache.ways], + (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", + (c->dcache.flags & MIPS_CACHE_ALIASES) ? "cache aliases" : "no aliases", - c->dcache.linesz); + c->dcache.linesz); } static void probe_vcache(void) diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c index 686867270627..2d479cc7e66b 100644 --- a/arch/mips/mm/c-tx39.c +++ b/arch/mips/mm/c-tx39.c @@ -410,9 +410,9 @@ void tx39_cache_init(void) current_cpu_data.icache.waybit = 0; current_cpu_data.dcache.waybit = 0; - printk("Primary instruction cache %ldkB, linesize %d bytes\n", + pr_info("Primary instruction cache %ldkB, linesize %d bytes\n", icache_size >> 10, current_cpu_data.icache.linesz); - printk("Primary data cache %ldkB, linesize %d bytes\n", + pr_info("Primary data cache %ldkB, linesize %d bytes\n", dcache_size >> 10, current_cpu_data.dcache.linesz); build_clear_page(); diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 344e6e9ea43b..da407cdc2135 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -1480,6 +1480,7 @@ static void build_r4000_tlb_refill_handler(void) static void setup_pw(void) { + unsigned int pwctl; unsigned long pgd_i, pgd_w; #ifndef __PAGETABLE_PMD_FOLDED unsigned long pmd_i, pmd_w; @@ -1506,6 +1507,7 @@ static void setup_pw(void) pte_i = ilog2(_PAGE_GLOBAL); pte_w = 0; + pwctl = 1 << 30; /* Set PWDirExt */ #ifndef __PAGETABLE_PMD_FOLDED write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i); @@ -1516,8 +1518,9 @@ static void setup_pw(void) #endif #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT - write_c0_pwctl(1 << 6 | psn); + pwctl |= (1 << 6 | psn); #endif + write_c0_pwctl(pwctl); write_c0_kpgd((long)swapper_pg_dir); kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */ } diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index a840e0c1642c..03d85b2b3eea 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -144,12 +144,6 @@ static irqreturn_t corehi_handler(int irq, void *dev_id) return IRQ_HANDLED; } -static struct irqaction corehi_irqaction = { - .handler = corehi_handler, - .name = "CoreHi", - .flags = IRQF_NO_THREAD, -}; - static msc_irqmap_t msc_irqmap[] __initdata = { {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0}, {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0}, @@ -223,5 +217,7 @@ void __init arch_init_irq(void) corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI; } - setup_irq(corehi_irq, &corehi_irqaction); + if (request_irq(corehi_irq, corehi_handler, IRQF_NO_THREAD, "CoreHi", + NULL)) + pr_err("Failed to request irq %d (CoreHi)\n", corehi_irq); } diff --git a/arch/mips/netlogic/xlr/fmn.c b/arch/mips/netlogic/xlr/fmn.c index d428e8471eec..d7db1533889a 100644 --- a/arch/mips/netlogic/xlr/fmn.c +++ b/arch/mips/netlogic/xlr/fmn.c @@ -110,12 +110,6 @@ static irqreturn_t fmn_message_handler(int irq, void *data) return IRQ_HANDLED; } -struct irqaction fmn_irqaction = { - .handler = fmn_message_handler, - .flags = IRQF_PERCPU, - .name = "fmn", -}; - void xlr_percpu_fmn_init(void) { struct xlr_fmn_info *cpu_fmn_info; @@ -195,8 +189,9 @@ void nlm_setup_fmn_irq(void) { uint32_t flags; - /* setup irq only once */ - setup_irq(IRQ_FMN, &fmn_irqaction); + /* request irq only once */ + if (request_irq(IRQ_FMN, fmn_message_handler, IRQF_PERCPU, "fmn", NULL)) + pr_err("Failed to request irq %d (fmn)\n", IRQ_FMN); flags = nlm_cop2_enable_irqsave(); nlm_fmn_setup_intr(IRQ_FMN, (1 << nlm_threads_per_core) - 1); diff --git a/arch/mips/pic32/pic32mzda/time.c b/arch/mips/pic32/pic32mzda/time.c index 905ec1d86928..7174e9abbb1b 100644 --- a/arch/mips/pic32/pic32mzda/time.c +++ b/arch/mips/pic32/pic32mzda/time.c @@ -3,11 +3,11 @@ * Joshua Henderson <joshua.henderson@microchip.com> * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. */ -#include <linux/clk-provider.h> #include <linux/clocksource.h> #include <linux/init.h> #include <linux/irqdomain.h> #include <linux/of.h> +#include <linux/of_clk.h> #include <linux/of_irq.h> #include <asm/time.h> @@ -23,7 +23,7 @@ static const struct of_device_id pic32_infra_match[] = { static unsigned int pic32_xlate_core_timer_irq(void) { - static struct device_node *node; + struct device_node *node; unsigned int irq; node = of_find_matching_node(NULL, pic32_infra_match); diff --git a/arch/mips/pistachio/time.c b/arch/mips/pistachio/time.c index 3c9235c7710a..de64751dec40 100644 --- a/arch/mips/pistachio/time.c +++ b/arch/mips/pistachio/time.c @@ -6,10 +6,10 @@ */ #include <linux/clk.h> -#include <linux/clk-provider.h> #include <linux/clocksource.h> #include <linux/init.h> #include <linux/of.h> +#include <linux/of_clk.h> #include <asm/mips-cps.h> #include <asm/time.h> diff --git a/arch/mips/pmcs-msp71xx/msp_irq.c b/arch/mips/pmcs-msp71xx/msp_irq.c index 8d53d7a2ed45..d525cc931d89 100644 --- a/arch/mips/pmcs-msp71xx/msp_irq.c +++ b/arch/mips/pmcs-msp71xx/msp_irq.c @@ -107,18 +107,6 @@ asmlinkage void plat_irq_dispatch(void) do_IRQ(MSP_INT_SW1); } -static struct irqaction cic_cascade_msp = { - .handler = no_action, - .name = "MSP CIC cascade", - .flags = IRQF_NO_THREAD, -}; - -static struct irqaction per_cascade_msp = { - .handler = no_action, - .name = "MSP PER cascade", - .flags = IRQF_NO_THREAD, -}; - void __init arch_init_irq(void) { /* assume we'll be using vectored interrupt mode except in UP mode*/ @@ -142,8 +130,12 @@ void __init arch_init_irq(void) #endif /* CONFIG_MIPS_MT_SMP */ #endif /* CONFIG_MIPS_MT */ /* setup the cascaded interrupts */ - setup_irq(MSP_INT_CIC, &cic_cascade_msp); - setup_irq(MSP_INT_PER, &per_cascade_msp); + if (request_irq(MSP_INT_CIC, no_action, IRQF_NO_THREAD, + "MSP CIC cascade", NULL)) + pr_err("Failed to register MSP CIC cascade interrupt\n"); + if (request_irq(MSP_INT_PER, no_action, IRQF_NO_THREAD, + "MSP PER cascade", NULL)) + pr_err("Failed to register MSP PER cascade interrupt\n"); #else /* @@ -153,7 +145,11 @@ void __init arch_init_irq(void) msp_slp_irq_init(); /* setup the cascaded SLP/PER interrupts */ - setup_irq(MSP_INT_SLP, &cic_cascade_msp); - setup_irq(MSP_INT_PER, &per_cascade_msp); + if (request_irq(MSP_INT_SLP, no_action, IRQF_NO_THREAD, + "MSP CIC cascade", NULL)) + pr_err("Failed to register MSP CIC cascade interrupt\n"); + if (request_irq(MSP_INT_PER, no_action, IRQF_NO_THREAD, + "MSP PER cascade", NULL)) + pr_err("Failed to register MSP PER cascade interrupt\n"); #endif } diff --git a/arch/mips/pmcs-msp71xx/msp_smp.c b/arch/mips/pmcs-msp71xx/msp_smp.c index 8f00d26f2a53..00092e2924ec 100644 --- a/arch/mips/pmcs-msp71xx/msp_smp.c +++ b/arch/mips/pmcs-msp71xx/msp_smp.c @@ -38,21 +38,10 @@ static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static struct irqaction irq_resched = { - .handler = ipi_resched_interrupt, - .flags = IRQF_PERCPU, - .name = "IPI_resched" -}; - -static struct irqaction irq_call = { - .handler = ipi_call_interrupt, - .flags = IRQF_PERCPU, - .name = "IPI_call" -}; - -void __init arch_init_ipiirq(int irq, struct irqaction *action) +void __init arch_init_ipiirq(int irq, const char *name, irq_handler_t handler) { - setup_irq(irq, action); + if (request_irq(irq, handler, IRQF_PERCPU, name, NULL)) + pr_err("Failed to request irq %d (%s)\n", irq, name); irq_set_handler(irq, handle_percpu_irq); } @@ -60,7 +49,8 @@ void __init msp_vsmp_int_init(void) { set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); - arch_init_ipiirq(MIPS_CPU_IPI_RESCHED_IRQ, &irq_resched); - arch_init_ipiirq(MIPS_CPU_IPI_CALL_IRQ, &irq_call); + arch_init_ipiirq(MIPS_CPU_IPI_RESCHED_IRQ, "IPI_resched", + ipi_resched_interrupt); + arch_init_ipiirq(MIPS_CPU_IPI_CALL_IRQ, "IPI_call", ipi_call_interrupt); } #endif /* CONFIG_MIPS_MT_SMP */ diff --git a/arch/mips/pmcs-msp71xx/msp_time.c b/arch/mips/pmcs-msp71xx/msp_time.c index d83de01f00b8..9c629829f447 100644 --- a/arch/mips/pmcs-msp71xx/msp_time.c +++ b/arch/mips/pmcs-msp71xx/msp_time.c @@ -27,7 +27,6 @@ #define get_current_vpe() \ ((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE) -static struct irqaction timer_vpe1; static int tim_installed; void __init plat_time_init(void) @@ -77,10 +76,13 @@ void __init plat_time_init(void) unsigned int get_c0_compare_int(void) { + unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED; + /* MIPS_MT modes may want timer for second VPE */ if ((get_current_vpe()) && !tim_installed) { - memcpy(&timer_vpe1, &c0_compare_irqaction, sizeof(timer_vpe1)); - setup_irq(MSP_INT_VPE1_TIMER, &timer_vpe1); + if (request_irq(MSP_INT_VPE1_TIMER, c0_compare_interrupt, flags, + "timer", c0_compare_interrupt)) + pr_err("Failed to register timer interrupt\n"); tim_installed++; } diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig index 94e9ce994494..35c2ebd8f094 100644 --- a/arch/mips/ralink/Kconfig +++ b/arch/mips/ralink/Kconfig @@ -52,6 +52,7 @@ choice select COMMON_CLK select CLKSRC_MIPS_GIC select HAVE_PCI if PCI_MT7621 + select SOC_BUS endchoice choice diff --git a/arch/mips/ralink/cevt-rt3352.c b/arch/mips/ralink/cevt-rt3352.c index 61a08943eb2f..269d4877d120 100644 --- a/arch/mips/ralink/cevt-rt3352.c +++ b/arch/mips/ralink/cevt-rt3352.c @@ -82,12 +82,6 @@ static struct systick_device systick = { }, }; -static struct irqaction systick_irqaction = { - .handler = systick_interrupt, - .flags = IRQF_PERCPU | IRQF_TIMER, - .dev_id = &systick.dev, -}; - static int systick_shutdown(struct clock_event_device *evt) { struct systick_device *sdev; @@ -95,7 +89,7 @@ static int systick_shutdown(struct clock_event_device *evt) sdev = container_of(evt, struct systick_device, dev); if (sdev->irq_requested) - free_irq(systick.dev.irq, &systick_irqaction); + free_irq(systick.dev.irq, &systick.dev); sdev->irq_requested = 0; iowrite32(0, systick.membase + SYSTICK_CONFIG); @@ -104,12 +98,17 @@ static int systick_shutdown(struct clock_event_device *evt) static int systick_set_oneshot(struct clock_event_device *evt) { + const char *name = systick.dev.name; struct systick_device *sdev; + int irq = systick.dev.irq; sdev = container_of(evt, struct systick_device, dev); - if (!sdev->irq_requested) - setup_irq(systick.dev.irq, &systick_irqaction); + if (!sdev->irq_requested) { + if (request_irq(irq, systick_interrupt, + IRQF_PERCPU | IRQF_TIMER, name, &systick.dev)) + pr_err("Failed to request irq %d (%s)\n", irq, name); + } sdev->irq_requested = 1; iowrite32(CFG_EXT_STK_EN | CFG_CNT_EN, systick.membase + SYSTICK_CONFIG); @@ -125,7 +124,6 @@ static int __init ralink_systick_init(struct device_node *np) if (!systick.membase) return -ENXIO; - systick_irqaction.name = np->name; systick.dev.name = np->name; clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60); systick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev); diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c index 9415be0d57b8..0accb80db709 100644 --- a/arch/mips/ralink/mt7621.c +++ b/arch/mips/ralink/mt7621.c @@ -7,6 +7,8 @@ #include <linux/kernel.h> #include <linux/init.h> +#include <linux/slab.h> +#include <linux/sys_soc.h> #include <asm/mipsregs.h> #include <asm/smp-ops.h> @@ -160,6 +162,33 @@ void __init ralink_of_remap(void) panic("Failed to remap core resources"); } +static void soc_dev_init(struct ralink_soc_info *soc_info, u32 rev) +{ + struct soc_device *soc_dev; + struct soc_device_attribute *soc_dev_attr; + + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return; + + soc_dev_attr->soc_id = "mt7621"; + soc_dev_attr->family = "Ralink"; + + if (((rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK) == 1 && + (rev & CHIP_REV_ECO_MASK) == 1) + soc_dev_attr->revision = "E2"; + else + soc_dev_attr->revision = "E1"; + + soc_dev_attr->data = soc_info; + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) { + kfree(soc_dev_attr); + return; + } +} + void prom_soc_init(struct ralink_soc_info *soc_info) { void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE); @@ -214,6 +243,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info) rt2880_pinmux_data = mt7621_pinmux_data; + soc_dev_init(soc_info, rev); if (!register_cps_smp_ops()) return; diff --git a/arch/mips/ralink/timer-gic.c b/arch/mips/ralink/timer-gic.c index 944fbe0fc741..dcf2a44ac51e 100644 --- a/arch/mips/ralink/timer-gic.c +++ b/arch/mips/ralink/timer-gic.c @@ -8,7 +8,7 @@ #include <linux/init.h> #include <linux/of.h> -#include <linux/clk-provider.h> +#include <linux/of_clk.h> #include <linux/clocksource.h> #include "common.h" diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c index a0a79222ce0b..f3b0e90e0135 100644 --- a/arch/mips/sgi-ip22/ip22-eisa.c +++ b/arch/mips/sgi-ip22/ip22-eisa.c @@ -92,11 +92,6 @@ static irqreturn_t ip22_eisa_intr(int irq, void *dev_id) return IRQ_NONE; } -static struct irqaction eisa_action = { - .handler = ip22_eisa_intr, - .name = "EISA", -}; - int __init ip22_eisa_init(void) { int i, c; @@ -136,9 +131,8 @@ int __init ip22_eisa_init(void) init_i8259_irqs(); - /* Cannot use request_irq because of kmalloc not being ready at such - * an early stage. Yes, I've been bitten... */ - setup_irq(SGI_EISA_IRQ, &eisa_action); + if (request_irq(SGI_EISA_IRQ, ip22_eisa_intr, 0, "EISA", NULL)) + pr_err("Failed to request irq %d (EISA)\n", SGI_EISA_IRQ); EISA_bus = 1; return 0; diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c index 3804895fa697..96798a4ab2de 100644 --- a/arch/mips/sgi-ip22/ip22-int.c +++ b/arch/mips/sgi-ip22/ip22-int.c @@ -159,36 +159,7 @@ static void __irq_entry indy_buserror_irq(void) irq_exit(); } -static struct irqaction local0_cascade = { - .handler = no_action, - .flags = IRQF_NO_THREAD, - .name = "local0 cascade", -}; - -static struct irqaction local1_cascade = { - .handler = no_action, - .flags = IRQF_NO_THREAD, - .name = "local1 cascade", -}; - -static struct irqaction buserr = { - .handler = no_action, - .flags = IRQF_NO_THREAD, - .name = "Bus Error", -}; - -static struct irqaction map0_cascade = { - .handler = no_action, - .flags = IRQF_NO_THREAD, - .name = "mapable0 cascade", -}; - #ifdef USE_LIO3_IRQ -static struct irqaction map1_cascade = { - .handler = no_action, - .flags = IRQF_NO_THREAD, - .name = "mapable1 cascade", -}; #define SGI_INTERRUPTS SGINT_END #else #define SGI_INTERRUPTS SGINT_LOCAL3 @@ -322,14 +293,24 @@ void __init arch_init_irq(void) } /* vector handler. this register the IRQ as non-sharable */ - setup_irq(SGI_LOCAL_0_IRQ, &local0_cascade); - setup_irq(SGI_LOCAL_1_IRQ, &local1_cascade); - setup_irq(SGI_BUSERR_IRQ, &buserr); + if (request_irq(SGI_LOCAL_0_IRQ, no_action, IRQF_NO_THREAD, + "local0 cascade", NULL)) + pr_err("Failed to register local0 cascade interrupt\n"); + if (request_irq(SGI_LOCAL_1_IRQ, no_action, IRQF_NO_THREAD, + "local1 cascade", NULL)) + pr_err("Failed to register local1 cascade interrupt\n"); + if (request_irq(SGI_BUSERR_IRQ, no_action, IRQF_NO_THREAD, + "Bus Error", NULL)) + pr_err("Failed to register Bus Error interrupt\n"); /* cascade in cascade. i love Indy ;-) */ - setup_irq(SGI_MAP_0_IRQ, &map0_cascade); + if (request_irq(SGI_MAP_0_IRQ, no_action, IRQF_NO_THREAD, + "mapable0 cascade", NULL)) + pr_err("Failed to register mapable0 cascade interrupt\n"); #ifdef USE_LIO3_IRQ - setup_irq(SGI_MAP_1_IRQ, &map1_cascade); + if (request_irq(SGI_MAP_1_IRQ, no_action, IRQF_NO_THREAD, + "mapable1 cascade", NULL)) + pr_err("Failed to register mapable1 cascade interrupt\n"); #endif #ifdef CONFIG_EISA diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c index a6a0ff7f5aed..1bbd5bfb5458 100644 --- a/arch/mips/sgi-ip32/ip32-irq.c +++ b/arch/mips/sgi-ip32/ip32-irq.c @@ -111,16 +111,6 @@ static inline void flush_mace_bus(void) extern irqreturn_t crime_memerr_intr(int irq, void *dev_id); extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); -static struct irqaction memerr_irq = { - .handler = crime_memerr_intr, - .name = "CRIME memory error", -}; - -static struct irqaction cpuerr_irq = { - .handler = crime_cpuerr_intr, - .name = "CRIME CPU error", -}; - /* * This is for pure CRIME interrupts - ie not MACE. The advantage? * We get to split the register in half and do faster lookups. @@ -497,8 +487,12 @@ void __init arch_init_irq(void) break; } } - setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); - setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); + if (request_irq(CRIME_MEMERR_IRQ, crime_memerr_intr, 0, + "CRIME memory error", NULL)) + pr_err("Failed to register CRIME memory error interrupt\n"); + if (request_irq(CRIME_CPUERR_IRQ, crime_cpuerr_intr, 0, + "CRIME CPU error", NULL)) + pr_err("Failed to register CRIME CPU error interrupt\n"); #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) change_c0_status(ST0_IM, ALLINTS); diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c index f9407e170476..0ecffb65fd6d 100644 --- a/arch/mips/sni/a20r.c +++ b/arch/mips/sni/a20r.c @@ -222,7 +222,9 @@ void __init sni_a20r_irq_init(void) irq_set_chip_and_handler(i, &a20r_irq_type, handle_level_irq); sni_hwint = a20r_hwint; change_c0_status(ST0_IM, IE_IRQ0); - setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq); + if (request_irq(SNI_A20R_IRQ_BASE + 3, sni_isa_irq_handler, 0, "ISA", + NULL)) + pr_err("Failed to register ISA interrupt\n"); } void sni_a20r_init(void) diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c index ac61b90bcc66..dec89afc9886 100644 --- a/arch/mips/sni/irq.c +++ b/arch/mips/sni/irq.c @@ -27,7 +27,7 @@ asmlinkage void plat_irq_dispatch(void) } /* ISA irq handler */ -static irqreturn_t sni_isa_irq_handler(int dummy, void *p) +irqreturn_t sni_isa_irq_handler(int dummy, void *p) { int irq; @@ -39,12 +39,6 @@ static irqreturn_t sni_isa_irq_handler(int dummy, void *p) return IRQ_HANDLED; } -struct irqaction sni_isa_irq = { - .handler = sni_isa_irq_handler, - .name = "ISA", - .flags = IRQF_SHARED -}; - /* * On systems with i8259-style interrupt controllers we assume for * driver compatibility reasons interrupts 0 - 15 to be the i8295 diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c index 05bb51676e82..b331fe22c529 100644 --- a/arch/mips/sni/pcit.c +++ b/arch/mips/sni/pcit.c @@ -244,7 +244,9 @@ void __init sni_pcit_irq_init(void) *(volatile u32 *)SNI_PCIT_INT_REG = 0; sni_hwint = sni_pcit_hwint; change_c0_status(ST0_IM, IE_IRQ1); - setup_irq(SNI_PCIT_INT_START + 6, &sni_isa_irq); + if (request_irq(SNI_PCIT_INT_START + 6, sni_isa_irq_handler, 0, "ISA", + NULL)) + pr_err("Failed to register ISA interrupt\n"); } void __init sni_pcit_cplus_irq_init(void) @@ -257,7 +259,9 @@ void __init sni_pcit_cplus_irq_init(void) *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000; sni_hwint = sni_pcit_hwint_cplus; change_c0_status(ST0_IM, IE_IRQ0); - setup_irq(MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq); + if (request_irq(MIPS_CPU_IRQ_BASE + 3, sni_isa_irq_handler, 0, "ISA", + NULL)) + pr_err("Failed to register ISA interrupt\n"); } void __init sni_pcit_init(void) diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c index f6fa9afcbfd3..d84744ca871d 100644 --- a/arch/mips/sni/rm200.c +++ b/arch/mips/sni/rm200.c @@ -356,11 +356,6 @@ void sni_rm200_init_8259A(void) /* * IRQ2 is cascade interrupt to second interrupt controller */ -static struct irqaction sni_rm200_irq2 = { - .handler = no_action, - .name = "cascade", - .flags = IRQF_NO_THREAD, -}; static struct resource sni_rm200_pic1_resource = { .name = "onboard ISA pic1", @@ -389,12 +384,6 @@ static irqreturn_t sni_rm200_i8259A_irq_handler(int dummy, void *p) return IRQ_HANDLED; } -struct irqaction sni_rm200_i8259A_irq = { - .handler = sni_rm200_i8259A_irq_handler, - .name = "onboard ISA", - .flags = IRQF_SHARED -}; - void __init sni_rm200_i8259_irqs(void) { int i; @@ -417,7 +406,9 @@ void __init sni_rm200_i8259_irqs(void) irq_set_chip_and_handler(i, &sni_rm200_i8259A_chip, handle_level_irq); - setup_irq(RM200_I8259A_IRQ_BASE + PIC_CASCADE_IR, &sni_rm200_irq2); + if (request_irq(RM200_I8259A_IRQ_BASE + PIC_CASCADE_IR, no_action, + IRQF_NO_THREAD, "cascade", NULL)) + pr_err("Failed to register cascade interrupt\n"); } @@ -481,8 +472,12 @@ void __init sni_rm200_irq_init(void) irq_set_chip_and_handler(i, &rm200_irq_type, handle_level_irq); sni_hwint = sni_rm200_hwint; change_c0_status(ST0_IM, IE_IRQ0); - setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq); - setup_irq(SNI_RM200_INT_START + 1, &sni_isa_irq); + if (request_irq(SNI_RM200_INT_START + 0, sni_rm200_i8259A_irq_handler, + 0, "onboard ISA", NULL)) + pr_err("Failed to register onboard ISA interrupt\n"); + if (request_irq(SNI_RM200_INT_START + 1, sni_isa_irq_handler, 0, "ISA", + NULL)) + pr_err("Failed to register ISA interrupt\n"); } void __init sni_rm200_init(void) diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c index dbace1f3e1a9..240bb68ec247 100644 --- a/arch/mips/sni/time.c +++ b/arch/mips/sni/time.c @@ -55,12 +55,6 @@ static irqreturn_t a20r_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static struct irqaction a20r_irqaction = { - .handler = a20r_interrupt, - .flags = IRQF_PERCPU | IRQF_TIMER, - .name = "a20r-timer", -}; - /* * a20r platform uses 2 counters to divide the input frequency. * Counter 2 output is connected to Counter 0 & 1 input. @@ -68,13 +62,13 @@ static struct irqaction a20r_irqaction = { static void __init sni_a20r_timer_setup(void) { struct clock_event_device *cd = &a20r_clockevent_device; - struct irqaction *action = &a20r_irqaction; unsigned int cpu = smp_processor_id(); cd->cpumask = cpumask_of(cpu); clockevents_register_device(cd); - action->dev_id = cd; - setup_irq(SNI_A20R_IRQ_TIMER, &a20r_irqaction); + if (request_irq(SNI_A20R_IRQ_TIMER, a20r_interrupt, + IRQF_PERCPU | IRQF_TIMER, "a20r-timer", cd)) + pr_err("Failed to register a20r-timer interrupt\n"); } #define SNI_8254_TICK_RATE 1193182UL diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c index 7a826fbf9060..8f68446ff2d9 100644 --- a/arch/mips/vr41xx/common/irq.c +++ b/arch/mips/vr41xx/common/irq.c @@ -17,12 +17,6 @@ typedef struct irq_cascade { static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned; -static struct irqaction cascade_irqaction = { - .handler = no_action, - .name = "cascade", - .flags = IRQF_NO_THREAD, -}; - int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int)) { int retval = 0; @@ -36,7 +30,8 @@ int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int)) irq_cascade[irq].get_irq = get_irq; if (get_irq != NULL) { - retval = setup_irq(irq, &cascade_irqaction); + retval = request_irq(irq, no_action, IRQF_NO_THREAD, + "cascade", NULL); if (retval < 0) irq_cascade[irq].get_irq = NULL; } diff --git a/drivers/firmware/dmi_scan.c b/drivers/firmware/dmi_scan.c index 2045566d622f..f59163cb7cba 100644 --- a/drivers/firmware/dmi_scan.c +++ b/drivers/firmware/dmi_scan.c @@ -11,6 +11,10 @@ #include <asm/dmi.h> #include <asm/unaligned.h> +#ifndef SMBIOS_ENTRY_POINT_SCAN_START +#define SMBIOS_ENTRY_POINT_SCAN_START 0xF0000 +#endif + struct kobject *dmi_kobj; EXPORT_SYMBOL_GPL(dmi_kobj); @@ -663,7 +667,7 @@ static void __init dmi_scan_machine(void) return; } } else if (IS_ENABLED(CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK)) { - p = dmi_early_remap(0xF0000, 0x10000); + p = dmi_early_remap(SMBIOS_ENTRY_POINT_SCAN_START, 0x10000); if (p == NULL) goto error; diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig index 1c227ea8ecd3..593f149c2910 100644 --- a/drivers/ide/Kconfig +++ b/drivers/ide/Kconfig @@ -662,23 +662,6 @@ config BLK_DEV_IDE_PMAC_ATA100FIRST CD-ROM on hda. This option changes this to more natural hda for hard disk and hdc for CD-ROM. -config BLK_DEV_IDE_AU1XXX - bool "IDE for AMD Alchemy Au1200" - depends on MIPS_ALCHEMY - select IDE_XFER_MODE -choice - prompt "IDE Mode for AMD Alchemy Au1200" - default BLK_DEV_IDE_AU1XXX_PIO_DBDMA - depends on BLK_DEV_IDE_AU1XXX - -config BLK_DEV_IDE_AU1XXX_PIO_DBDMA - bool "PIO+DbDMA IDE for AMD Alchemy Au1200" - -config BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA - bool "MDMA2+DbDMA IDE for AMD Alchemy Au1200" - depends on BLK_DEV_IDE_AU1XXX -endchoice - config BLK_DEV_IDE_TX4938 tristate "TX4938 internal IDE support" depends on SOC_TX4938 @@ -859,8 +842,7 @@ config BLK_DEV_UMC8672 endif config BLK_DEV_IDEDMA - def_bool BLK_DEV_IDEDMA_SFF || \ - BLK_DEV_IDEDMA_ICS || BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA + def_bool BLK_DEV_IDEDMA_SFF || BLK_DEV_IDEDMA_ICS select IDE_XFER_MODE endif # IDE diff --git a/drivers/ide/Makefile b/drivers/ide/Makefile index d4f4409cfb8b..2605b3cdaf47 100644 --- a/drivers/ide/Makefile +++ b/drivers/ide/Makefile @@ -107,7 +107,5 @@ obj-$(CONFIG_BLK_DEV_IDE_ICSIDE) += icside.o obj-$(CONFIG_BLK_DEV_IDE_RAPIDE) += rapide.o obj-$(CONFIG_BLK_DEV_PALMCHIP_BK3710) += palm_bk3710.o -obj-$(CONFIG_BLK_DEV_IDE_AU1XXX) += au1xxx-ide.o - obj-$(CONFIG_BLK_DEV_IDE_TX4938) += tx4938ide.o obj-$(CONFIG_BLK_DEV_IDE_TX4939) += tx4939ide.o diff --git a/drivers/ide/au1xxx-ide.c b/drivers/ide/au1xxx-ide.c deleted file mode 100644 index 4d181a918d72..000000000000 --- a/drivers/ide/au1xxx-ide.c +++ /dev/null @@ -1,597 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * AMD Alchemy Au1xxx IDE interface routines over the Static Bus - * - * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your option) any later - * version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE - * Interface and Linux Device Driver" Application Note. - */ -#include <linux/types.h> -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/delay.h> -#include <linux/platform_device.h> -#include <linux/init.h> -#include <linux/ide.h> -#include <linux/scatterlist.h> - -#include <asm/mach-au1x00/au1000.h> -#include <asm/mach-au1x00/au1xxx_dbdma.h> -#include <asm/mach-au1x00/au1xxx_ide.h> - -#define DRV_NAME "au1200-ide" -#define DRV_AUTHOR "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>" - -#ifndef IDE_REG_SHIFT -#define IDE_REG_SHIFT 5 -#endif - -/* enable the burstmode in the dbdma */ -#define IDE_AU1XXX_BURSTMODE 1 - -static _auide_hwif auide_hwif; - -#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA) - -static inline void auide_insw(unsigned long port, void *addr, u32 count) -{ - _auide_hwif *ahwif = &auide_hwif; - chan_tab_t *ctp; - au1x_ddma_desc_t *dp; - - if (!au1xxx_dbdma_put_dest(ahwif->rx_chan, virt_to_phys(addr), - count << 1, DDMA_FLAGS_NOIE)) { - printk(KERN_ERR "%s failed %d\n", __func__, __LINE__); - return; - } - ctp = *((chan_tab_t **)ahwif->rx_chan); - dp = ctp->cur_ptr; - while (dp->dscr_cmd0 & DSCR_CMD0_V) - ; - ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp); -} - -static inline void auide_outsw(unsigned long port, void *addr, u32 count) -{ - _auide_hwif *ahwif = &auide_hwif; - chan_tab_t *ctp; - au1x_ddma_desc_t *dp; - - if (!au1xxx_dbdma_put_source(ahwif->tx_chan, virt_to_phys(addr), - count << 1, DDMA_FLAGS_NOIE)) { - printk(KERN_ERR "%s failed %d\n", __func__, __LINE__); - return; - } - ctp = *((chan_tab_t **)ahwif->tx_chan); - dp = ctp->cur_ptr; - while (dp->dscr_cmd0 & DSCR_CMD0_V) - ; - ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp); -} - -static void au1xxx_input_data(ide_drive_t *drive, struct ide_cmd *cmd, - void *buf, unsigned int len) -{ - auide_insw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2); -} - -static void au1xxx_output_data(ide_drive_t *drive, struct ide_cmd *cmd, - void *buf, unsigned int len) -{ - auide_outsw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2); -} -#endif - -static void au1xxx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) -{ - int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2); - - switch (drive->pio_mode - XFER_PIO_0) { - case 0: - mem_sttime = SBC_IDE_TIMING(PIO0); - - /* set configuration for RCS2# */ - mem_stcfg |= TS_MASK; - mem_stcfg &= ~TCSOE_MASK; - mem_stcfg &= ~TOECS_MASK; - mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS; - break; - - case 1: - mem_sttime = SBC_IDE_TIMING(PIO1); - - /* set configuration for RCS2# */ - mem_stcfg |= TS_MASK; - mem_stcfg &= ~TCSOE_MASK; - mem_stcfg &= ~TOECS_MASK; - mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS; - break; - - case 2: - mem_sttime = SBC_IDE_TIMING(PIO2); - - /* set configuration for RCS2# */ - mem_stcfg &= ~TS_MASK; - mem_stcfg &= ~TCSOE_MASK; - mem_stcfg &= ~TOECS_MASK; - mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS; - break; - - case 3: - mem_sttime = SBC_IDE_TIMING(PIO3); - - /* set configuration for RCS2# */ - mem_stcfg &= ~TS_MASK; - mem_stcfg &= ~TCSOE_MASK; - mem_stcfg &= ~TOECS_MASK; - mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS; - - break; - - case 4: - mem_sttime = SBC_IDE_TIMING(PIO4); - - /* set configuration for RCS2# */ - mem_stcfg &= ~TS_MASK; - mem_stcfg &= ~TCSOE_MASK; - mem_stcfg &= ~TOECS_MASK; - mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS; - break; - } - - au_writel(mem_sttime,MEM_STTIME2); - au_writel(mem_stcfg,MEM_STCFG2); -} - -static void auide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) -{ - int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2); - - switch (drive->dma_mode) { -#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA - case XFER_MW_DMA_2: - mem_sttime = SBC_IDE_TIMING(MDMA2); - - /* set configuration for RCS2# */ - mem_stcfg &= ~TS_MASK; - mem_stcfg &= ~TCSOE_MASK; - mem_stcfg &= ~TOECS_MASK; - mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS; - - break; - case XFER_MW_DMA_1: - mem_sttime = SBC_IDE_TIMING(MDMA1); - - /* set configuration for RCS2# */ - mem_stcfg &= ~TS_MASK; - mem_stcfg &= ~TCSOE_MASK; - mem_stcfg &= ~TOECS_MASK; - mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS; - - break; - case XFER_MW_DMA_0: - mem_sttime = SBC_IDE_TIMING(MDMA0); - - /* set configuration for RCS2# */ - mem_stcfg |= TS_MASK; - mem_stcfg &= ~TCSOE_MASK; - mem_stcfg &= ~TOECS_MASK; - mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS; - - break; -#endif - } - - au_writel(mem_sttime,MEM_STTIME2); - au_writel(mem_stcfg,MEM_STCFG2); -} - -/* - * Multi-Word DMA + DbDMA functions - */ - -#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA -static int auide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd) -{ - ide_hwif_t *hwif = drive->hwif; - _auide_hwif *ahwif = &auide_hwif; - struct scatterlist *sg; - int i = cmd->sg_nents, count = 0; - int iswrite = !!(cmd->tf_flags & IDE_TFLAG_WRITE); - - /* Save for interrupt context */ - ahwif->drive = drive; - - /* fill the descriptors */ - sg = hwif->sg_table; - while (i && sg_dma_len(sg)) { - u32 cur_addr; - u32 cur_len; - - cur_addr = sg_dma_address(sg); - cur_len = sg_dma_len(sg); - - while (cur_len) { - u32 flags = DDMA_FLAGS_NOIE; - unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00; - - if (++count >= PRD_ENTRIES) { - printk(KERN_WARNING "%s: DMA table too small\n", - drive->name); - return 0; - } - - /* Lets enable intr for the last descriptor only */ - if (1==i) - flags = DDMA_FLAGS_IE; - else - flags = DDMA_FLAGS_NOIE; - - if (iswrite) { - if (!au1xxx_dbdma_put_source(ahwif->tx_chan, - sg_phys(sg), tc, flags)) { - printk(KERN_ERR "%s failed %d\n", - __func__, __LINE__); - } - } else { - if (!au1xxx_dbdma_put_dest(ahwif->rx_chan, - sg_phys(sg), tc, flags)) { - printk(KERN_ERR "%s failed %d\n", - __func__, __LINE__); - } - } - - cur_addr += tc; - cur_len -= tc; - } - sg = sg_next(sg); - i--; - } - - if (count) - return 1; - - return 0; /* revert to PIO for this request */ -} - -static int auide_dma_end(ide_drive_t *drive) -{ - return 0; -} - -static void auide_dma_start(ide_drive_t *drive ) -{ -} - - -static int auide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd) -{ - if (auide_build_dmatable(drive, cmd) == 0) - return 1; - - return 0; -} - -static int auide_dma_test_irq(ide_drive_t *drive) -{ - /* If dbdma didn't execute the STOP command yet, the - * active bit is still set - */ - drive->waiting_for_dma++; - if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) { - printk(KERN_WARNING "%s: timeout waiting for ddma to complete\n", - drive->name); - return 1; - } - udelay(10); - return 0; -} - -static void auide_dma_host_set(ide_drive_t *drive, int on) -{ -} - -static void auide_ddma_tx_callback(int irq, void *param) -{ -} - -static void auide_ddma_rx_callback(int irq, void *param) -{ -} -#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */ - -static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, - u32 devwidth, u32 flags, u32 regbase) -{ - dev->dev_id = dev_id; - dev->dev_physaddr = CPHYSADDR(regbase); - dev->dev_intlevel = 0; - dev->dev_intpolarity = 0; - dev->dev_tsize = tsize; - dev->dev_devwidth = devwidth; - dev->dev_flags = flags; -} - -#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA -static const struct ide_dma_ops au1xxx_dma_ops = { - .dma_host_set = auide_dma_host_set, - .dma_setup = auide_dma_setup, - .dma_start = auide_dma_start, - .dma_end = auide_dma_end, - .dma_test_irq = auide_dma_test_irq, - .dma_lost_irq = ide_dma_lost_irq, -}; - -static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d) -{ - _auide_hwif *auide = &auide_hwif; - dbdev_tab_t source_dev_tab, target_dev_tab; - u32 dev_id, tsize, devwidth, flags; - - dev_id = hwif->ddma_id; - - tsize = 8; /* 1 */ - devwidth = 32; /* 16 */ - -#ifdef IDE_AU1XXX_BURSTMODE - flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE; -#else - flags = DEV_FLAGS_SYNC; -#endif - - /* setup dev_tab for tx channel */ - auide_init_dbdma_dev(&source_dev_tab, dev_id, tsize, devwidth, - DEV_FLAGS_OUT | flags, auide->regbase); - auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); - - auide_init_dbdma_dev(&source_dev_tab, dev_id, tsize, devwidth, - DEV_FLAGS_IN | flags, auide->regbase); - auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); - - /* We also need to add a target device for the DMA */ - auide_init_dbdma_dev(&target_dev_tab, (u32)DSCR_CMD0_ALWAYS, tsize, - devwidth, DEV_FLAGS_ANYUSE, auide->regbase); - auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab); - - /* Get a channel for TX */ - auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id, - auide->tx_dev_id, - auide_ddma_tx_callback, - (void*)auide); - - /* Get a channel for RX */ - auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id, - auide->target_dev_id, - auide_ddma_rx_callback, - (void*)auide); - - auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan, - NUM_DESCRIPTORS); - auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan, - NUM_DESCRIPTORS); - - /* FIXME: check return value */ - (void)ide_allocate_dma_engine(hwif); - - au1xxx_dbdma_start( auide->tx_chan ); - au1xxx_dbdma_start( auide->rx_chan ); - - return 0; -} -#else -static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d) -{ - _auide_hwif *auide = &auide_hwif; - dbdev_tab_t source_dev_tab; - int flags; - -#ifdef IDE_AU1XXX_BURSTMODE - flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE; -#else - flags = DEV_FLAGS_SYNC; -#endif - - /* setup dev_tab for tx channel */ - auide_init_dbdma_dev(&source_dev_tab, (u32)DSCR_CMD0_ALWAYS, 8, 32, - DEV_FLAGS_OUT | flags, auide->regbase); - auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); - - auide_init_dbdma_dev(&source_dev_tab, (u32)DSCR_CMD0_ALWAYS, 8, 32, - DEV_FLAGS_IN | flags, auide->regbase); - auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); - - /* Get a channel for TX */ - auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS, - auide->tx_dev_id, - NULL, - (void*)auide); - - /* Get a channel for RX */ - auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id, - DSCR_CMD0_ALWAYS, - NULL, - (void*)auide); - - auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan, - NUM_DESCRIPTORS); - auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan, - NUM_DESCRIPTORS); - - au1xxx_dbdma_start( auide->tx_chan ); - au1xxx_dbdma_start( auide->rx_chan ); - - return 0; -} -#endif - -static void auide_setup_ports(struct ide_hw *hw, _auide_hwif *ahwif) -{ - int i; - unsigned long *ata_regs = hw->io_ports_array; - - /* FIXME? */ - for (i = 0; i < 8; i++) - *ata_regs++ = ahwif->regbase + (i << IDE_REG_SHIFT); - - /* set the Alternative Status register */ - *ata_regs = ahwif->regbase + (14 << IDE_REG_SHIFT); -} - -#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA -static const struct ide_tp_ops au1xxx_tp_ops = { - .exec_command = ide_exec_command, - .read_status = ide_read_status, - .read_altstatus = ide_read_altstatus, - .write_devctl = ide_write_devctl, - - .dev_select = ide_dev_select, - .tf_load = ide_tf_load, - .tf_read = ide_tf_read, - - .input_data = au1xxx_input_data, - .output_data = au1xxx_output_data, -}; -#endif - -static const struct ide_port_ops au1xxx_port_ops = { - .set_pio_mode = au1xxx_set_pio_mode, - .set_dma_mode = auide_set_dma_mode, -}; - -static const struct ide_port_info au1xxx_port_info = { - .init_dma = auide_ddma_init, -#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA - .tp_ops = &au1xxx_tp_ops, -#endif - .port_ops = &au1xxx_port_ops, -#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA - .dma_ops = &au1xxx_dma_ops, -#endif - .host_flags = IDE_HFLAG_POST_SET_MODE | - IDE_HFLAG_NO_IO_32BIT | - IDE_HFLAG_UNMASK_IRQS, - .pio_mask = ATA_PIO4, -#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA - .mwdma_mask = ATA_MWDMA2, -#endif - .chipset = ide_au1xxx, -}; - -static int au_ide_probe(struct platform_device *dev) -{ - _auide_hwif *ahwif = &auide_hwif; - struct resource *res; - struct ide_host *host; - int ret = 0; - struct ide_hw hw, *hws[] = { &hw }; - -#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA) - char *mode = "MWDMA2"; -#elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA) - char *mode = "PIO+DDMA(offload)"; -#endif - - memset(&auide_hwif, 0, sizeof(_auide_hwif)); - ahwif->irq = platform_get_irq(dev, 0); - - res = platform_get_resource(dev, IORESOURCE_MEM, 0); - - if (res == NULL) { - pr_debug("%s %d: no base address\n", DRV_NAME, dev->id); - ret = -ENODEV; - goto out; - } - if (ahwif->irq < 0) { - pr_debug("%s %d: no IRQ\n", DRV_NAME, dev->id); - ret = -ENODEV; - goto out; - } - - if (!request_mem_region(res->start, resource_size(res), dev->name)) { - pr_debug("%s: request_mem_region failed\n", DRV_NAME); - ret = -EBUSY; - goto out; - } - - ahwif->regbase = (u32)ioremap(res->start, resource_size(res)); - if (ahwif->regbase == 0) { - ret = -ENOMEM; - goto out; - } - - res = platform_get_resource(dev, IORESOURCE_DMA, 0); - if (!res) { - pr_debug("%s: no DDMA ID resource\n", DRV_NAME); - ret = -ENODEV; - goto out; - } - ahwif->ddma_id = res->start; - - memset(&hw, 0, sizeof(hw)); - auide_setup_ports(&hw, ahwif); - hw.irq = ahwif->irq; - hw.dev = &dev->dev; - - ret = ide_host_add(&au1xxx_port_info, hws, 1, &host); - if (ret) - goto out; - - auide_hwif.hwif = host->ports[0]; - - platform_set_drvdata(dev, host); - - printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode ); - - out: - return ret; -} - -static int au_ide_remove(struct platform_device *dev) -{ - struct resource *res; - struct ide_host *host = platform_get_drvdata(dev); - _auide_hwif *ahwif = &auide_hwif; - - ide_host_remove(host); - - iounmap((void *)ahwif->regbase); - - res = platform_get_resource(dev, IORESOURCE_MEM, 0); - release_mem_region(res->start, resource_size(res)); - - return 0; -} - -static struct platform_driver au1200_ide_driver = { - .driver = { - .name = "au1200-ide", - }, - .probe = au_ide_probe, - .remove = au_ide_remove, -}; - -module_platform_driver(au1200_ide_driver); - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("AU1200 IDE driver"); diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 24fe08702ef7..a85aada04a64 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -513,4 +513,23 @@ config EXYNOS_IRQ_COMBINER Say yes here to add support for the IRQ combiner devices embedded in Samsung Exynos chips. +config LOONGSON_LIOINTC + bool "Loongson Local I/O Interrupt Controller" + depends on MACH_LOONGSON64 + default y + select IRQ_DOMAIN + select GENERIC_IRQ_CHIP + help + Support for the Loongson Local I/O Interrupt Controller. + +config LOONGSON_HTPIC + bool "Loongson3 HyperTransport PIC Controller" + depends on MACH_LOONGSON64 + default y + select IRQ_DOMAIN + select GENERIC_IRQ_CHIP + select I8259 + help + Support for the Loongson-3 HyperTransport PIC Controller. + endmenu diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index eae0d78cbf22..37bbe39bf909 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -105,3 +105,5 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o +obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o +obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o diff --git a/drivers/irqchip/irq-loongson-htpic.c b/drivers/irqchip/irq-loongson-htpic.c new file mode 100644 index 000000000000..dd018c22ea83 --- /dev/null +++ b/drivers/irqchip/irq-loongson-htpic.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com> + * Loongson HTPIC IRQ support + */ + +#include <linux/init.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/irqchip.h> +#include <linux/irqchip/chained_irq.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/syscore_ops.h> + +#include <asm/i8259.h> + +#define HTPIC_MAX_PARENT_IRQ 4 +#define HTINT_NUM_VECTORS 8 +#define HTINT_EN_OFF 0x20 + +struct loongson_htpic { + void __iomem *base; + struct irq_domain *domain; +}; + +static struct loongson_htpic *htpic; + +static void htpic_irq_dispatch(struct irq_desc *desc) +{ + struct loongson_htpic *priv = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + uint32_t pending; + + chained_irq_enter(chip, desc); + pending = readl(priv->base); + /* Ack all IRQs at once, otherwise IRQ flood might happen */ + writel(pending, priv->base); + + if (!pending) + spurious_interrupt(); + + while (pending) { + int bit = __ffs(pending); + + if (unlikely(bit > 15)) { + spurious_interrupt(); + break; + } + + generic_handle_irq(irq_linear_revmap(priv->domain, bit)); + pending &= ~BIT(bit); + } + chained_irq_exit(chip, desc); +} + +static void htpic_reg_init(void) +{ + int i; + + for (i = 0; i < HTINT_NUM_VECTORS; i++) { + uint32_t val; + + /* Disable all HT Vectors */ + writel(0x0, htpic->base + HTINT_EN_OFF + i * 0x4); + val = readl(htpic->base + i * 0x4); + /* Ack all possible pending IRQs */ + writel(GENMASK(31, 0), htpic->base + i * 0x4); + } + + /* Enable 16 vectors for PIC */ + writel(0xffff, htpic->base + HTINT_EN_OFF); +} + +static void htpic_resume(void) +{ + htpic_reg_init(); +} + +struct syscore_ops htpic_syscore_ops = { + .resume = htpic_resume, +}; + +int __init htpic_of_init(struct device_node *node, struct device_node *parent) +{ + unsigned int parent_irq[4]; + int i, err; + int num_parents = 0; + + if (htpic) { + pr_err("loongson-htpic: Only one HTPIC is allowed in the system\n"); + return -ENODEV; + } + + htpic = kzalloc(sizeof(*htpic), GFP_KERNEL); + if (!htpic) { + err = -ENOMEM; + goto out_free; + } + + htpic->base = of_iomap(node, 0); + if (!htpic->base) { + err = -ENODEV; + goto out_free; + } + + htpic->domain = __init_i8259_irqs(node); + if (!htpic->domain) { + pr_err("loongson-htpic: Failed to initialize i8259 IRQs\n"); + err = -ENOMEM; + goto out_iounmap; + } + + /* Interrupt may come from any of the 4 interrupt line */ + for (i = 0; i < HTPIC_MAX_PARENT_IRQ; i++) { + parent_irq[i] = irq_of_parse_and_map(node, i); + if (parent_irq[i] <= 0) + break; + + num_parents++; + } + + if (!num_parents) { + pr_err("loongson-htpic: Failed to get parent irqs\n"); + err = -ENODEV; + goto out_remove_domain; + } + + htpic_reg_init(); + + for (i = 0; i < num_parents; i++) { + irq_set_chained_handler_and_data(parent_irq[i], + htpic_irq_dispatch, htpic); + } + + register_syscore_ops(&htpic_syscore_ops); + + return 0; + +out_remove_domain: + irq_domain_remove(htpic->domain); +out_iounmap: + iounmap(htpic->base); +out_free: + kfree(htpic); + return err; +} + +IRQCHIP_DECLARE(loongson_htpic, "loongson,htpic-1.0", htpic_of_init); diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c new file mode 100644 index 000000000000..63b61474a0cc --- /dev/null +++ b/drivers/irqchip/irq-loongson-liointc.c @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com> + * Loongson Local IO Interrupt Controller support + */ + +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/irqchip.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/io.h> +#include <linux/smp.h> +#include <linux/irqchip/chained_irq.h> + +#include <boot_param.h> + +#define LIOINTC_CHIP_IRQ 32 +#define LIOINTC_NUM_PARENT 4 + +#define LIOINTC_INTC_CHIP_START 0x20 + +#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20) +#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04) +#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08) +#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c) +#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10) +#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14) + +#define LIOINTC_SHIFT_INTx 4 + +#define LIOINTC_ERRATA_IRQ 10 + +struct liointc_handler_data { + struct liointc_priv *priv; + u32 parent_int_map; +}; + +struct liointc_priv { + struct irq_chip_generic *gc; + struct liointc_handler_data handler[LIOINTC_NUM_PARENT]; + u8 map_cache[LIOINTC_CHIP_IRQ]; + bool has_lpc_irq_errata; +}; + +static void liointc_chained_handle_irq(struct irq_desc *desc) +{ + struct liointc_handler_data *handler = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct irq_chip_generic *gc = handler->priv->gc; + u32 pending; + + chained_irq_enter(chip, desc); + + pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS); + + if (!pending) { + /* Always blame LPC IRQ if we have that bug */ + if (handler->priv->has_lpc_irq_errata && + (handler->parent_int_map & ~gc->mask_cache & + BIT(LIOINTC_ERRATA_IRQ))) + pending = BIT(LIOINTC_ERRATA_IRQ); + else + spurious_interrupt(); + } + + while (pending) { + int bit = __ffs(pending); + + generic_handle_irq(irq_find_mapping(gc->domain, bit)); + pending &= ~BIT(bit); + } + + chained_irq_exit(chip, desc); +} + +static void liointc_set_bit(struct irq_chip_generic *gc, + unsigned int offset, + u32 mask, bool set) +{ + if (set) + writel(readl(gc->reg_base + offset) | mask, + gc->reg_base + offset); + else + writel(readl(gc->reg_base + offset) & ~mask, + gc->reg_base + offset); +} + +static int liointc_set_type(struct irq_data *data, unsigned int type) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); + u32 mask = data->mask; + unsigned long flags; + + irq_gc_lock_irqsave(gc, flags); + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false); + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true); + break; + case IRQ_TYPE_LEVEL_LOW: + liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false); + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false); + break; + case IRQ_TYPE_EDGE_RISING: + liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true); + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true); + break; + case IRQ_TYPE_EDGE_FALLING: + liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true); + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false); + break; + default: + return -EINVAL; + } + irq_gc_unlock_irqrestore(gc, flags); + + irqd_set_trigger_type(data, type); + return 0; +} + +static void liointc_resume(struct irq_chip_generic *gc) +{ + struct liointc_priv *priv = gc->private; + unsigned long flags; + int i; + + irq_gc_lock_irqsave(gc, flags); + /* Disable all at first */ + writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE); + /* Revert map cache */ + for (i = 0; i < LIOINTC_CHIP_IRQ; i++) + writeb(priv->map_cache[i], gc->reg_base + i); + /* Revert mask cache */ + writel(~gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE); + irq_gc_unlock_irqrestore(gc, flags); +} + +static const char * const parent_names[] = {"int0", "int1", "int2", "int3"}; + +int __init liointc_of_init(struct device_node *node, + struct device_node *parent) +{ + struct irq_chip_generic *gc; + struct irq_domain *domain; + struct irq_chip_type *ct; + struct liointc_priv *priv; + void __iomem *base; + u32 of_parent_int_map[LIOINTC_NUM_PARENT]; + int parent_irq[LIOINTC_NUM_PARENT]; + bool have_parent = FALSE; + int sz, i, err = 0; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + base = of_iomap(node, 0); + if (!base) { + err = -ENODEV; + goto out_free_priv; + } + + for (i = 0; i < LIOINTC_NUM_PARENT; i++) { + parent_irq[i] = of_irq_get_byname(node, parent_names[i]); + if (parent_irq[i] > 0) + have_parent = TRUE; + } + if (!have_parent) { + err = -ENODEV; + goto out_iounmap; + } + + sz = of_property_read_variable_u32_array(node, + "loongson,parent_int_map", + &of_parent_int_map[0], + LIOINTC_NUM_PARENT, + LIOINTC_NUM_PARENT); + if (sz < 4) { + pr_err("loongson-liointc: No parent_int_map\n"); + err = -ENODEV; + goto out_iounmap; + } + + for (i = 0; i < LIOINTC_NUM_PARENT; i++) + priv->handler[i].parent_int_map = of_parent_int_map[i]; + + /* Setup IRQ domain */ + domain = irq_domain_add_linear(node, 32, + &irq_generic_chip_ops, priv); + if (!domain) { + pr_err("loongson-liointc: cannot add IRQ domain\n"); + err = -EINVAL; + goto out_iounmap; + } + + err = irq_alloc_domain_generic_chips(domain, 32, 1, + node->full_name, handle_level_irq, + IRQ_NOPROBE, 0, 0); + if (err) { + pr_err("loongson-liointc: unable to register IRQ domain\n"); + goto out_free_domain; + } + + + /* Disable all IRQs */ + writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE); + /* Set to level triggered */ + writel(0x0, base + LIOINTC_REG_INTC_EDGE); + + /* Generate parent INT part of map cache */ + for (i = 0; i < LIOINTC_NUM_PARENT; i++) { + u32 pending = priv->handler[i].parent_int_map; + + while (pending) { + int bit = __ffs(pending); + + priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx; + pending &= ~BIT(bit); + } + } + + for (i = 0; i < LIOINTC_CHIP_IRQ; i++) { + /* Generate core part of map cache */ + priv->map_cache[i] |= BIT(loongson_sysconf.boot_cpu_id); + writeb(priv->map_cache[i], base + i); + } + + gc = irq_get_domain_generic_chip(domain, 0); + gc->private = priv; + gc->reg_base = base; + gc->domain = domain; + gc->resume = liointc_resume; + + ct = gc->chip_types; + ct->regs.enable = LIOINTC_REG_INTC_ENABLE; + ct->regs.disable = LIOINTC_REG_INTC_DISABLE; + ct->chip.irq_unmask = irq_gc_unmask_enable_reg; + ct->chip.irq_mask = irq_gc_mask_disable_reg; + ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; + ct->chip.irq_set_type = liointc_set_type; + + gc->mask_cache = 0xffffffff; + priv->gc = gc; + + for (i = 0; i < LIOINTC_NUM_PARENT; i++) { + if (parent_irq[i] <= 0) + continue; + + priv->handler[i].priv = priv; + irq_set_chained_handler_and_data(parent_irq[i], + liointc_chained_handle_irq, &priv->handler[i]); + } + + return 0; + +out_free_domain: + irq_domain_remove(domain); +out_iounmap: + iounmap(base); +out_free_priv: + kfree(priv); + + return err; +} + +IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init); +IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init); diff --git a/drivers/video/fbdev/g364fb.c b/drivers/video/fbdev/g364fb.c index 845b79da2a7c..05837a3b985c 100644 --- a/drivers/video/fbdev/g364fb.c +++ b/drivers/video/fbdev/g364fb.c @@ -108,7 +108,6 @@ static int g364fb_pan_display(struct fb_var_screeninfo *var, static int g364fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, u_int transp, struct fb_info *info); -static int g364fb_cursor(struct fb_info *info, struct fb_cursor *cursor); static int g364fb_blank(int blank, struct fb_info *info); static const struct fb_ops g364fb_ops = { @@ -119,28 +118,8 @@ static const struct fb_ops g364fb_ops = { .fb_fillrect = cfb_fillrect, .fb_copyarea = cfb_copyarea, .fb_imageblit = cfb_imageblit, - .fb_cursor = g364fb_cursor, }; -int g364fb_cursor(struct fb_info *info, struct fb_cursor *cursor) -{ - - switch (cursor->enable) { - case CM_ERASE: - *(unsigned int *) CTLA_REG |= CURS_TOGGLE; - break; - - case CM_MOVE: - case CM_DRAW: - *(unsigned int *) CTLA_REG &= ~CURS_TOGGLE; - *(unsigned int *) CURS_POS_REG = - ((x * fontwidth(p)) << 12) | ((y * fontheight(p)) - - info->var.yoffset); - break; - } - return 0; -} - /* * Pan or Wrap the Display * @@ -194,11 +173,9 @@ static int g364fb_setcolreg(u_int regno, u_int red, u_int green, */ int __init g364fb_init(void) { - volatile unsigned int *pal_ptr = - (volatile unsigned int *) CLR_PAL_REG; volatile unsigned int *curs_pal_ptr = (volatile unsigned int *) CURS_PAL_REG; - int mem, i, j; + int mem, i; if (fb_get_options("g364fb", NULL)) return -ENODEV; @@ -230,8 +207,8 @@ int __init g364fb_init(void) */ *(unsigned short *) (CURS_PAT_REG + 14 * 64) = 0xffff; *(unsigned short *) (CURS_PAT_REG + 15 * 64) = 0xffff; - fb_var.xres_virtual = fbvar.xres; - fb_fix.line_length = (xres / 8) * fb_var.bits_per_pixel; + fb_var.xres_virtual = fb_var.xres; + fb_fix.line_length = fb_var.xres_virtual * fb_var.bits_per_pixel / 8; fb_fix.smem_start = 0x40000000; /* physical address */ /* get size of video memory; this is special for the JAZZ hardware */ mem = (r4030_read_reg32(JAZZ_R4030_CONFIG) >> 8) & 3; |