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| author | Alex Deucher <alexander.deucher@amd.com> | 2014-10-15 17:20:55 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2014-10-16 18:34:09 -0400 |
| commit | 8e66e134e20b936179ea1535dd4ed19ec4f99dba (patch) | |
| tree | 72d79bcfa0252136570760964444792ecfb17a5e | |
| parent | e300180f71037fd9ed1ca967006fd9f3ee466bcd (diff) | |
| download | linux-8e66e134e20b936179ea1535dd4ed19ec4f99dba.tar.gz | |
drm/radeon: fix vm page table block size calculation
The page offset is 12 bits. For example if we have an 8 GB VM, we'd need 33 bits. The number of bits needed for PD + PT is 21 (33 - 12 or log2(8) + 18), not 20 (log2(8) + 17). Noticed by Alexey during code review. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_device.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 6fbab1582112..55065d844205 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -1126,7 +1126,7 @@ static void radeon_check_arguments(struct radeon_device *rdev) if (radeon_vm_block_size == -1) { /* Total bits covered by PD + PTs */ - unsigned bits = ilog2(radeon_vm_size) + 17; + unsigned bits = ilog2(radeon_vm_size) + 18; /* Make sure the PD is 4K in size up to 8GB address space. Above that split equal between PD and PTs */ |