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| author | Naveen Naidu <naveennaidu479@gmail.com> | 2021-11-18 19:33:11 +0530 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2021-11-18 13:18:07 -0600 |
| commit | 57bdeef4716689d9b0e3571034d65cf420f6efcd (patch) | |
| tree | cac89b7f67f8de256f2d2c01ec392b1ec195780b | |
| parent | fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf (diff) | |
| download | linux-57bdeef4716689d9b0e3571034d65cf420f6efcd.tar.gz | |
PCI: Add PCI_ERROR_RESPONSE and related definitions
A config or MMIO read from a PCI device that doesn't exist or doesn't respond causes a PCI error. There's no real data to return to satisfy the CPU read, so most hardware fabricates ~0 data. Add a PCI_ERROR_RESPONSE definition for that and use it where appropriate to make these checks consistent and easier to find. Also add helper definitions PCI_SET_ERROR_RESPONSE() and PCI_POSSIBLE_ERROR() to make the code more readable. Suggested-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/55563bf4dfc5d3fdc96695373c659d099bf175b1.1637243717.git.naveennaidu479@gmail.com Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pali Rohár <pali@kernel.org>
| -rw-r--r-- | include/linux/pci.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/linux/pci.h b/include/linux/pci.h index 18a75c8e615c..0ce26850470e 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -155,6 +155,15 @@ enum pci_interrupt_pin { #define PCI_NUM_INTX 4 /* + * Reading from a device that doesn't respond typically returns ~0. A + * successful read from a device may also return ~0, so you need additional + * information to reliably identify errors. + */ +#define PCI_ERROR_RESPONSE (~0ULL) +#define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) +#define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) + +/* * pci_power_t values must match the bits in the Capabilities PME_Support * and Control/Status PowerState fields in the Power Management capability. */ |