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| author | Swapnil Patel <swapatel@amd.com> | 2023-11-02 16:16:49 -0400 |
|---|---|---|
| committer | Joshua Ashton <joshua@froggi.es> | 2023-11-03 01:33:25 +0000 |
| commit | 36301114e8a32e7f13985cbbeff7282d4c599aed (patch) | |
| tree | 2fdc2cc8c0b51c9aa2e2ab62dd0b51348283336a | |
| parent | 32d8309584145f531b46e8c1a72c86494e72160d (diff) | |
| download | linux-36301114e8a32e7f13985cbbeff7282d4c599aed.tar.gz | |
Disable modes with >1200 MHz Pixel clocks when connected via dock
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/link/link_validation.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c index e8b2fc4002a5..3c69d860e1c9 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c @@ -35,6 +35,8 @@ #define DC_LOGGER_INIT(logger) +static const uint8_t DP_SINK_BRANCH_DEV_NAME_KT50X0[] = "KT50X0!"; + static uint32_t get_tmds_output_pixel_clock_100hz(const struct dc_crtc_timing *timing) { @@ -277,6 +279,15 @@ static bool dp_validate_mode_timing( timing->v_addressable == (uint32_t) 480) return true; + if (link->ctx->dce_version == DCN_VERSION_3_01 && + link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0060AD && + memcmp(&link->dpcd_caps.branch_dev_name, + DP_SINK_BRANCH_DEV_NAME_KT50X0, + sizeof(link->dpcd_caps.branch_dev_name)) == 0) { + if (timing->pix_clk_100hz / 10 >= (uint32_t) 1200000) + return false; /* KT50X0 does not support Pxl clock >= 1200MHz */ + } + link_setting = dp_get_verified_link_cap(link); /* TODO: DYNAMIC_VALIDATION needs to be implemented */ |