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| author | Gabriele Paoloni <gabriele.paoloni@huawei.com> | 2015-10-08 14:27:53 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2015-11-02 14:48:45 -0600 |
| commit | b6b18f589e1ddbfbc31f72ea7fb8a723a2d10058 (patch) | |
| tree | b3eed584ffa7dfc38ccb617ef5fc795741630bf1 | |
| parent | 4c45852f494dab827291c656ee9e12f3f4ee64d6 (diff) | |
| download | linux-b6b18f589e1ddbfbc31f72ea7fb8a723a2d10058.tar.gz | |
PCI: designware: Require config accesses to be naturally aligned
Add sanity checks on "addr" input parameter in dw_pcie_cfg_read() and dw_pcie_cfg_write(). These checks make sure that accesses are aligned on their size, e.g., a 4-byte config access is aligned on a 4-byte boundary. [bhelgaas: changelog, set *val = 0 in failure case] Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
| -rw-r--r-- | drivers/pci/host/pcie-designware.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 759cd0a50910..b77535f3967b 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -82,6 +82,11 @@ static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys) int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) { + if ((uintptr_t)addr & (size - 1)) { + *val = 0; + return PCIBIOS_BAD_REGISTER_NUMBER; + } + if (size == 4) *val = readl(addr); else if (size == 2) @@ -98,6 +103,9 @@ int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val) { + if ((uintptr_t)addr & (size - 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + if (size == 4) writel(val, addr); else if (size == 2) |