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| author | Jacopo Mondi <jacopo+renesas@jmondi.org> | 2018-09-17 07:30:56 -0400 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2018-10-04 14:49:17 -0400 |
| commit | a7f9d21e9e96dea2e41d82e08ea2a55afdadd741 (patch) | |
| tree | a17916880858728567981cba03913b29b087a985 | |
| parent | 6bc3ea7a61897b5e4dbb937b75febb8d9c06b8a5 (diff) | |
| download | linux-a7f9d21e9e96dea2e41d82e08ea2a55afdadd741.tar.gz | |
media: i2c: adv748x: Conditionally enable only CSI-2 outputs
The ADV748x has two CSI-2 output port and one TTL input/output port for digital video reception/transmission. The TTL digital pad is unconditionally enabled during the device reset even if not used. Same goes for the TXA and TXB CSI-2 outputs, which are enabled by the initial settings blob programmed into the chip. In order to improve power saving, do not enable unused output interfaces: keep TTL output disabled, as it is not used, and drop CSI-2 output enabling from the initial settings list, as they get conditionally enabled later. Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
| -rw-r--r-- | drivers/media/i2c/adv748x/adv748x-core.c | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/drivers/media/i2c/adv748x/adv748x-core.c b/drivers/media/i2c/adv748x/adv748x-core.c index aa9dbde9730a..806e1b24d3fd 100644 --- a/drivers/media/i2c/adv748x/adv748x-core.c +++ b/drivers/media/i2c/adv748x/adv748x-core.c @@ -382,8 +382,6 @@ static const struct adv748x_reg_value adv748x_init_txa_4lane[] = { {ADV748X_PAGE_IO, 0x0c, 0xe0}, /* Enable LLC_DLL & Double LLC Timing */ {ADV748X_PAGE_IO, 0x0e, 0xdd}, /* LLC/PIX/SPI PINS TRISTATED AUD */ - /* Outputs Enabled */ - {ADV748X_PAGE_IO, 0x10, 0xa0}, /* Enable 4-lane CSI Tx & Pixel Port */ {ADV748X_PAGE_TXA, 0x00, 0x84}, /* Enable 4-lane MIPI */ {ADV748X_PAGE_TXA, 0x00, 0xa4}, /* Set Auto DPHY Timing */ @@ -437,10 +435,6 @@ static const struct adv748x_reg_value adv748x_init_txb_1lane[] = { {ADV748X_PAGE_SDP, 0x31, 0x12}, /* ADI Required Write */ {ADV748X_PAGE_SDP, 0xe6, 0x4f}, /* V bit end pos manually in NTSC */ - /* Enable 1-Lane MIPI Tx, */ - /* enable pixel output and route SD through Pixel port */ - {ADV748X_PAGE_IO, 0x10, 0x70}, - {ADV748X_PAGE_TXB, 0x00, 0x81}, /* Enable 1-lane MIPI */ {ADV748X_PAGE_TXB, 0x00, 0xa1}, /* Set Auto DPHY Timing */ {ADV748X_PAGE_TXB, 0xd2, 0x40}, /* ADI Required Write */ @@ -465,7 +459,7 @@ static const struct adv748x_reg_value adv748x_init_txb_1lane[] = { static int adv748x_reset(struct adv748x_state *state) { int ret; - u8 regval = ADV748X_IO_10_PIX_OUT_EN; + u8 regval = 0; ret = adv748x_write_regs(state, adv748x_sw_reset); if (ret < 0) |