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| author | Jingoo Han <jg1.han@samsung.com> | 2012-11-09 15:56:03 +0900 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2012-11-09 11:17:59 -0700 |
| commit | b891b4dc1eed33543c5818dae43ce8bb55f2080c (patch) | |
| tree | dff8e2872e4cc018ed8e93bb529ebf305a4029aa | |
| parent | 6e965e0d0e1d102c261326b06338d3385ea55f97 (diff) | |
| download | linux-b891b4dc1eed33543c5818dae43ce8bb55f2080c.tar.gz | |
PCI: Fix bit definitions of PCI_EXP_LNKCAP2 register
According to the PCIe 3.0 spec, PCI_EXP_LNKCAP2_SLS_2_5GB is 1st bit of PCI_EXP_LNKCAP2 register, not 0th bit. So, the bit definition of supported link speed vector should be fixed. [bhelgaas: change "Current" to "Supported"] Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| -rw-r--r-- | include/uapi/linux/pci_regs.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 20ae747ddf34..259763d2df71 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -544,9 +544,9 @@ #define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */ #define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */ -#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */ -#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */ -#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x04 /* Current Link Speed 8.0GT/s */ +#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ +#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ +#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ #define PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */ #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ |